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34 lines
996 B
Verilog
34 lines
996 B
Verilog
module graphtest (A,B,X,Y,Z);
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input [3:0] A;
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input [3:0] B;
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output reg [3:0] X;
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output [9:0] Y;
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output [7:0] Z;
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wire [4:0] t;
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assign t[4] = 1'b0; // Constant connects to wire
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assign t[2:0] = A[2:0] & { 2'b10, B[3]}; // Concatenation of intermediate wire
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assign t[3] = A[2] ^ B[3]; // Bitwise-XOR
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// assign Y[2:0] = 3'b111;
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// assign Y[6:3] = A;
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// assign Y[9:7] = t[0:2];
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assign Y = {3'b111, A, t[2:0]}; // Direct assignment of concatenation
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assign Z[0] = 1'b0; // Constant connects to PO
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assign Z[1] = t[3]; // Intermediate sig connects to PO
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assign Z[3:2] = A[2:1]; // PI connects to PO
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assign Z[7:4] = {1'b0, B[2:0]}; // Concat of CV and PI connect to PO
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always @* begin
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if (A == 4'b1111) begin // All-Const at port (eq)
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X = B;
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end
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else begin
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X = 4'b0000; // All-Const at port (mux)
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end
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end
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endmodule
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