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			28 lines
		
	
	
	
		
			555 B
		
	
	
	
		
			Verilog
		
	
	
	
	
	
			
		
		
	
	
			28 lines
		
	
	
	
		
			555 B
		
	
	
	
		
			Verilog
		
	
	
	
	
	
| module attrib03_bar(clk, rst, inp, out);
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| 
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|   (* bus_width *)
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|   parameter WIDTH = 2;
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| 
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|   (* an_attribute_on_localparam = 55 *)
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|   localparam INCREMENT = 5;
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| 
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|   input  wire clk;
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|   input  wire rst;
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|   input  wire [WIDTH-1:0] inp;
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|   output reg  [WIDTH-1:0] out;
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| 
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|   always @(posedge clk)
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|     if (rst) out <= 0;
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|     else     out <= inp + INCREMENT;
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| 
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| endmodule
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| 
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| module attrib03_foo(clk, rst, inp, out);
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|   input  wire clk;
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|   input  wire rst;
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|   input  wire [7:0] inp;
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|   output wire [7:0] out;
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| 
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|   attrib03_bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out);
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| endmodule
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| 
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