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15 lines
217 B
Verilog
15 lines
217 B
Verilog
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module array_test001(a, b, c, y);
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input a;
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input [31:0] b, c;
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output [31:0] y;
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aoi12 p [31:0] (a, b, c, y);
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endmodule
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module aoi12(a, b, c, y);
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input a, b, c;
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output y;
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assign y = ~((a & b) | c);
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endmodule
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