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yosys/tests/sim/vcd_var_reference_whitespace.ys
Miodrag Milanovic 48a3dcc02a End of file fix
2026-06-23 07:23:41 +02:00

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read_rtlil vector_assign.il
sim -r var_reference_without_whitespace.vcd -scope tb.uut
sim -r var_reference_with_whitespace.vcd -scope tb.uut