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2e37e62e6b
By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
49 lines
1 KiB
Verilog
49 lines
1 KiB
Verilog
// DATAIN: synchronous data input
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// CLK: clock input (positive edge)
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// ACLR: asynchronous clear (negative-true)
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// ENA: clock-enable
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// SCLR: synchronous clear
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// SLOAD: synchronous load
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// SDATA: synchronous load data
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//
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// Q: data output
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//
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// Note: the DFFEAS primitive is mostly emulated; it does not reflect what the hardware implements.
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module MISTRAL_FF(
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input DATAIN, CLK, ACLR, ENA, SCLR, SLOAD, SDATA,
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output reg Q
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);
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`ifdef cyclonev
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specify
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(posedge CLK => (Q : DATAIN)) = 262;
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$setup(DATAIN, posedge CLK, 522);
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endspecify
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`endif
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`ifdef cyclone10gx
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specify
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(posedge CLK => (Q : DATAIN)) = 219;
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$setup(DATAIN, posedge CLK, 268);
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endspecify
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`endif
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initial begin
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// Altera flops initialise to zero.
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Q = 0;
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end
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always @(posedge CLK, negedge ACLR) begin
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// Asynchronous clear
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if (!ACLR) Q <= 0;
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// Clock-enable
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else if (ENA) begin
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// Synchronous clear
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if (SCLR) Q <= 0;
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// Synchronous load
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else if (SLOAD) Q <= SDATA;
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else Q <= DATAIN;
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end
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end
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endmodule
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