| abc9_map.v | quicklogic: ABC9 synthesis | 2021-04-17 20:54:58 +02:00 | 
		
			
			
			
			
				| abc9_model.v | quicklogic: ABC9 synthesis | 2021-04-17 20:54:58 +02:00 | 
		
			
			
			
			
				| abc9_unmap.v | quicklogic: ABC9 synthesis | 2021-04-17 20:54:58 +02:00 | 
		
			
			
			
			
				| cells_sim.v | quicklogic: PolarPro 3 support | 2021-03-18 13:28:16 +01:00 | 
		
			
			
			
			
				| lut_sim.v | quicklogic: PolarPro 3 support | 2021-03-18 13:28:16 +01:00 | 
		
			
			
			
			
				| Makefile.inc | quicklogic: ABC9 synthesis | 2021-04-17 20:54:58 +02:00 | 
		
			
			
			
			
				| pp3_cells_map.v | quicklogic: PolarPro 3 support | 2021-03-18 13:28:16 +01:00 | 
		
			
			
			
			
				| pp3_cells_sim.v | quicklogic: ABC9 synthesis | 2021-04-17 20:54:58 +02:00 | 
		
			
			
			
			
				| pp3_ffs_map.v | quicklogic: PolarPro 3 support | 2021-03-18 13:28:16 +01:00 | 
		
			
			
			
			
				| pp3_latches_map.v | quicklogic: PolarPro 3 support | 2021-03-18 13:28:16 +01:00 | 
		
			
			
			
			
				| pp3_lut_map.v | quicklogic: PolarPro 3 support | 2021-03-18 13:28:16 +01:00 | 
		
			
			
			
			
				| synth_quicklogic.cc | quicklogic: ABC9 synthesis | 2021-04-17 20:54:58 +02:00 |