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https://github.com/YosysHQ/yosys
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43 lines
1.8 KiB
Text
43 lines
1.8 KiB
Text
read_verilog -D NO_INIT ../common/adffs.v
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design -save read
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hierarchy -top adff
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proc
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equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adff # Constrain all select calls below inside the top module
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select -assert-count 1 t:CC_BUFG
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select -assert-count 1 t:CC_DFF
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select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D
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design -load read
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hierarchy -top adffn
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proc
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equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adffn # Constrain all select calls below inside the top module
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select -assert-count 1 t:CC_BUFG
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select -assert-count 1 t:CC_DFF
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select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D
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design -load read
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hierarchy -top dffs
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proc
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equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffs # Constrain all select calls below inside the top module
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select -assert-count 1 t:CC_BUFG
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select -assert-count 1 t:CC_DFF
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select -assert-max 1 t:CC_LUT2
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select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D
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design -load read
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hierarchy -top ndffnr
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proc
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equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd ndffnr # Constrain all select calls below inside the top module
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select -assert-count 1 t:CC_BUFG
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select -assert-count 1 t:CC_DFF
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select -assert-max 1 t:CC_LUT2
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select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D
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