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yosys/passes
Emil J. Tywoniak 436d698525 refactor
2025-08-15 12:19:03 +02:00
..
cmds fixup! HACK to unconditionally debug bufnorm drivers in show output 2025-08-14 17:18:51 +02:00
equiv equiv_simple: Avoid std::array 2025-08-08 12:37:38 +12:00
fsm refactor 2025-08-15 12:19:03 +02:00
hierarchy Reapply "Add groups to command reference" 2025-08-06 13:52:12 +12:00
memory ast, read_verilog: ownership in AST, use C++ styles for parser and lexer 2025-08-11 13:34:10 +02:00
opt WIP add placeholder $connect cell 2025-08-14 16:12:53 +02:00
pmgen Reapply "Add groups to command reference" 2025-08-06 13:52:12 +12:00
proc Proc: Use selections consistently 2025-05-31 12:04:42 +12:00
sat Reapply "Add groups to command reference" 2025-08-06 13:52:12 +12:00
techmap Reapply "Add groups to command reference" 2025-08-06 13:52:12 +12:00
tests test_cell: Add comment on $pmux 2025-08-12 10:57:59 +12:00