mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-28 19:35:53 +00:00
213 lines
7.5 KiB
C++
213 lines
7.5 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* 2024 Alain Dargelas <alain@silimate.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct ActivityProp {
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Module *module;
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SigMap sigmap;
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uint32_t nbBitsWithActivity = 0;
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// Split a string based on separator, returns a vector of tokens as reference argument
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// If skipEmpty is true, return "" for string " ", when separator is " "
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void tokenize(std::string_view str, std::string_view separator, std::vector<std::string> &result, bool skipEmpty)
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{
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std::string::size_type pos{0};
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const auto sepSize = separator.size();
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const auto stringSize = str.size();
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std::string tmp;
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std::string::size_type n = str.find(separator, pos);
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while (n != std::string::npos) {
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tmp = str.substr(pos, n - pos);
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if (!(tmp.empty() && skipEmpty))
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result.push_back(tmp);
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pos = n + sepSize;
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n = str.find(separator, pos);
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}
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if (pos < stringSize) { // put last part
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tmp = str.substr(pos, stringSize - pos);
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if (!(tmp.empty() && skipEmpty))
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result.push_back(tmp);
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}
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}
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// Split a string based on separator, returns a vector of tokens
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// If skipEmpty is true, return "" for string " ", when separator is " "
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std::vector<std::string> tokenize(std::string_view str, std::string_view separator, bool skipEmpty)
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{
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std::vector<std::string> result;
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tokenize(str, separator, result, skipEmpty);
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return result;
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}
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ActivityProp(Module *module) : module(module), sigmap(module)
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{
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std::map<SigBit, std::string> ActivityMap;
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std::map<SigBit, std::string> DutyMap;
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// Build {signal bit - activity} map from the wire activities calculated in the sim pass
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for (Wire *wire : module->wires()) {
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SigSpec sig(sigmap(wire));
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// Retrieve the activity/dutycycle attributes created in the sim pass, attached to wires, in the form:
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// $ACKT: 0.1 0.2 .... (Each bit in a bus has its own activity, index 0 of the bus is left most)
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std::string act = wire->get_string_attribute("$ACKT");
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std::string duty = wire->get_string_attribute("$DUTY");
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//std::cout << "WIRE: " << wire->name.c_str() << " act: " << act << std::endl;
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// Split the activity lists
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std::vector<std::string> activities = tokenize(act, " ", true);
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std::vector<std::string> duties = tokenize(duty, " ", true);
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// Assign them to each SigBit (1 signal bit)
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for (uint32_t i = 0; i < (uint32_t)GetSize(sig); i++) {
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SigBit bit(sig[i]);
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if (i < activities.size()) {
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ActivityMap.emplace(bit, activities[i]);
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DutyMap.emplace(bit, duties[i]);
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nbBitsWithActivity++;
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} else {
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log_warning("Zeroing out activity for module: %s, wire: %s, wire_size: %d, activ_size: %ld\n",
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module->name.c_str(), wire->name.c_str(), GetSize(sig), activities.size());
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ActivityMap.emplace(bit, "0.0");
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DutyMap.emplace(bit, "0.0");
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}
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}
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}
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// Attach port activity to cell using sigmap
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for (auto cell : module->cells()) {
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std::string cell_ports_activity;
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std::string cell_ports_duty;
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for (auto conn : cell->connections()) {
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// Recombine individual bit activities for all cell ports into a list attached to the cell
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for (int i = 0; i < GetSize(conn.second); i++) {
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SigBit bit(sigmap(conn.second[i]));
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std::string port_name = std::string(conn.first.c_str()) + "[" + std::to_string(i) + "]";
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{
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std::map<SigBit, std::string>::iterator itr = ActivityMap.find(bit);
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if (itr != ActivityMap.end()) {
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cell_ports_activity += port_name + "=" + (*itr).second + " ";
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} else {
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RTLIL::SigSpec sigspec(bit);
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if (!sigspec.is_fully_const()) {
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log_warning("No activity found for : %s/%s/%s\n", module->name.c_str(), cell->name.c_str(), port_name.c_str());
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}
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// constants have no activity
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cell_ports_activity += port_name + "=" + "0.0 ";
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}
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}
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{
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std::map<SigBit, std::string>::iterator itr = DutyMap.find(bit);
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if (itr != DutyMap.end()) {
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cell_ports_duty += port_name + "=" + (*itr).second + " ";
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} else {
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RTLIL::SigSpec sigspec(bit);
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if (!sigspec.is_fully_const()) {
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log_warning("No dutycycle found for : %s/%s/%s\n", module->name.c_str(), cell->name.c_str(), port_name.c_str());
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}
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// constant 1 has duty cycle 1, constant 0 has duty cycle 0
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cell_ports_duty += port_name + "=" + (sigspec.as_bool() ? "1.0" : "0.0") + " ";
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}
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}
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}
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}
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// Annotate on cells the complete list of ports activities and dutycycles in the form:
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// $ACKT: \P1=0.1 \P2=0.2 ....
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cell->set_string_attribute("$ACKT:", cell_ports_activity);
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cell->set_string_attribute("$DUTY:", cell_ports_duty);
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}
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}
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uint32_t getNbBitsWithActivity() { return nbBitsWithActivity; }
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};
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struct ActivityClear {
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Module *module;
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ActivityClear(Module *module) : module(module)
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{
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for (Wire *wire : module->wires()) {
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wire->set_string_attribute("$ACKT", "");
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wire->set_string_attribute("$DUTY", "");
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}
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for (auto cell : module->cells()) {
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cell->set_string_attribute("$ACKT:", "");
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cell->set_string_attribute("$DUTY:", "");
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}
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}
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};
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struct ActivityPropPass : public Pass {
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ActivityPropPass() : Pass("activity_prop", "Attaches wire activity to cell ports") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" activity_prop\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing Activity propagation pass\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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// No options currently. When adding in the future make sure to update docstring with [options]
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break;
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}
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extra_args(args, argidx, design);
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uint32_t totalNbBitsWithActivity = 0;
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for (auto module : design->modules()) {
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ActivityProp worker(module);
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totalNbBitsWithActivity += worker.getNbBitsWithActivity();
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}
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log("Collected %d bits with activity\n", totalNbBitsWithActivity);
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log_flush();
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}
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} ActivityPropPass;
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struct ActivityClearPass : public Pass {
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ActivityClearPass() : Pass("activity_clear", "Clears activity attached to cells and wires") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" activity_clear\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing Activity clearing pass\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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// No options currently. When adding in the future make sure to update docstring with [options]
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->modules()) {
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ActivityClear worker(module);
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}
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}
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} ActivityClearPass;
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PRIVATE_NAMESPACE_END
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