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46 lines
664 B
Plaintext
46 lines
664 B
Plaintext
read_rtlil << EOT
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module \top
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wire width 4 input 0 \S
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wire width 5 output 1 \Y
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cell $bmux $0
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parameter \WIDTH 5
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parameter \S_WIDTH 4
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connect \A 80'10110100011101110001110010001110101010111000110011111111111110100000110100111000
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connect \S \S
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connect \Y \Y
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end
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end
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EOT
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hierarchy -auto-top
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equiv_opt -assert bmuxmap -pmux
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###
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design -reset
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read_rtlil << EOT
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module \top
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wire width 10 input 0 \A
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wire input 1 \S
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wire width 5 output 2 \Y
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cell $bmux $0
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parameter \WIDTH 5
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parameter \S_WIDTH 1
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connect \A \A
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connect \S \S
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connect \Y \Y
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end
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end
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EOT
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hierarchy -auto-top
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equiv_opt -assert bmuxmap -pmux
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