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yosys/backends/verilog
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whitequark 42c47a83da write_verilog: escape names that match SystemVerilog keywords.
2019-01-27 00:03:53 +00:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc write_verilog: escape names that match SystemVerilog keywords. 2019-01-27 00:03:53 +00:00