Emil J. Tywoniak f27309136f Revert "verilog: fix string literal regular expression (#5187)" ... This reverts commit 834a7294b7.		2025-08-11 13:34:10 +02:00
..
.gitignore	Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.	2025-07-22 10:38:38 +00:00
absurd_width.ys
absurd_width_const.ys
always_comb_latch_1.ys
always_comb_latch_2.ys
always_comb_latch_3.ys
always_comb_latch_4.ys
always_comb_nolatch_1.ys
always_comb_nolatch_2.ys
always_comb_nolatch_3.ys
always_comb_nolatch_4.ys
always_comb_nolatch_5.ys
always_comb_nolatch_6.ys
asgn_expr.sv
asgn_expr.ys
asgn_expr_not_proc_1.ys
asgn_expr_not_proc_2.ys
asgn_expr_not_proc_3.ys
asgn_expr_not_proc_4.ys
asgn_expr_not_proc_5.ys
asgn_expr_not_sv_1.ys
asgn_expr_not_sv_2.ys
asgn_expr_not_sv_3.ys
asgn_expr_not_sv_4.ys
assign_to_reg.ys	Remove references to ilang	2024-11-05 12:36:31 +13:00
atom_type_signedness.ys
block_end_label_only.ys
block_end_label_wrong.ys
block_labels.ys
bug656.v
bug656.ys
bug2037.ys
bug2042-sv.ys
bug2042.ys
bug2493.ys
bug4785.ys	simplify: Skip AST_PRIMITIVE in AST_CELLARRAY	2025-03-25 12:15:54 +13:00
conflict_assert.ys
conflict_cell_memory.ys
conflict_interface_port.ys
conflict_memory_wire.ys
conflict_pwire.ys
conflict_wire_memory.ys
const_arst.ys
const_sr.ys
constparser_f.ys	fixup! const2ast: add diagnostics tests	2025-06-16 22:50:31 +02:00
constparser_f_file.sv	const2ast: add diagnostics tests	2025-06-16 21:48:12 +02:00
constparser_f_file.ys	const2ast: add diagnostics tests	2025-06-16 21:48:12 +02:00
constparser_g.ys	const2ast: add diagnostics tests	2025-06-16 21:48:12 +02:00
delay_mintypmax.ys
delay_risefall.ys
delay_time_scale.ys
doubleslash.ys
dynamic_range_lhs.sh
dynamic_range_lhs.v
for_decl_no_init.ys
for_decl_no_sv.ys
for_decl_shadow.sv
for_decl_shadow.ys
func_arg_mismatch_1.ys
func_arg_mismatch_2.ys
func_arg_mismatch_3.ys
func_arg_mismatch_4.ys
func_task_arg_copying.ys	tests: add tests for task/function argument input/output copying	2025-05-31 01:21:06 +01:00
func_tern_hint.sv
func_tern_hint.ys
func_typename_ret.sv
func_typename_ret.ys
func_upto.sv
func_upto.ys
gen_block_end_label_only.ys
gen_block_end_label_wrong.ys
genblk_case.v
genblk_case.ys
genblk_port_decl.ys
genfor_decl_no_init.ys
genfor_decl_no_sv.ys
genvar_loop_decl_1.sv
genvar_loop_decl_1.ys
genvar_loop_decl_2.sv
genvar_loop_decl_2.ys
genvar_loop_decl_3.sv
genvar_loop_decl_3.ys
global_parameter.ys
hidden_decl.ys
ifdef_nest.ys
ifdef_unterminated.ys
incdec.ys	tests: add tests for verilog pre/post increment/decrement in expressions	2025-05-30 14:38:25 +01:00
include_self.v
include_self.ys
int_types.sv
int_types.ys
localparam_no_default_1.ys
localparam_no_default_2.ys
macro_arg_tromp.sv
macro_arg_tromp.ys
macro_unapplied.ys
macro_unapplied_newline.ys
mem_bounds.sv
mem_bounds.ys
module_end_label.ys
net_types.sv
net_types.ys
package_end_label.ys
package_import_separate.sv	use more standard naming conventions	2025-08-06 15:39:30 -04:00
package_import_separate.ys	add newline - whitespace	2025-08-06 19:00:11 -04:00
package_import_separate_module.sv	use more standard naming conventions	2025-08-06 15:39:30 -04:00
package_task_func.sv
package_task_func.ys
param_default.ys	tests: Add default param test file	2025-05-05 10:18:52 +12:00
param_int_types.sv
param_int_types.ys
param_no_default.sv
param_no_default.ys
param_no_default_not_svmode.ys
param_no_default_unbound_1.ys
param_no_default_unbound_2.ys
param_no_default_unbound_3.ys
param_no_default_unbound_4.ys
param_no_default_unbound_5.ys
parameters_across_files.ys
past_signedness.ys
port_int_types.sv
port_int_types.ys
prefix.sv
prefix.ys
priority_if_enc.ys	Add semantic test cases for SystemVerilog priority/unique/unique0 "if".	2025-05-24 08:44:04 -06:00
roundtrip_proc.ys
run-test.sh	test: restore verific handling, nicer naming	2024-12-13 10:24:47 +01:00
sbvector.ys	verific: support single_bit_vector	2025-05-12 13:23:29 +02:00
sign_array_query.ys
size_cast.sv
size_cast.ys
struct_access.sv
struct_access.ys
task_attr.ys
typedef_across_files.ys
typedef_const_shadow.sv
typedef_const_shadow.ys
typedef_legacy_conflict.ys
unbased_unsized.sv
unbased_unsized.ys
unbased_unsized_shift.sv
unbased_unsized_shift.ys
unbased_unsized_tern.sv
unbased_unsized_tern.ys
unique0_if_enc.ys	Add semantic test cases for SystemVerilog priority/unique/unique0 "if".	2025-05-24 08:44:04 -06:00
unique_if.ys	Accept (and ignore) SystemVerilog unique/priority if.	2025-05-22 19:28:28 -06:00
unique_if_else.ys	Accept (and ignore) SystemVerilog unique/priority if.	2025-05-22 19:28:28 -06:00
unique_if_else_begin.ys	Accept (and ignore) SystemVerilog unique/priority if.	2025-05-22 19:28:28 -06:00
unique_if_enc.ys	Add semantic test cases for SystemVerilog priority/unique/unique0 "if".	2025-05-24 08:44:04 -06:00
unique_priority_case.ys	tests: add cases covering full_case and parallel_case semantics	2025-05-29 20:45:57 -06:00
unique_priority_if.ys	tests: add cases covering full_case and parallel_case semantics	2025-05-29 20:45:57 -06:00
unmatched_else.ys
unmatched_elsif.ys
unmatched_endif.ys
unmatched_endif_2.ys
unnamed_block.ys
unnamed_genblk.sv
unnamed_genblk.ys
unreachable_case_sign.ys
upto.ys
void_func.ys
wire_and_var.sv
wire_and_var.ys