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https://github.com/YosysHQ/yosys
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85 lines
1.2 KiB
Verilog
85 lines
1.2 KiB
Verilog
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module example001(a, y);
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input [15:0] a;
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output y;
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wire gt = a > 12345;
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wire lt = a < 12345;
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assign y = !gt && !lt;
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endmodule
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// ------------------------------------
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module example002(a, y);
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input [3:0] a;
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output y;
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reg [1:0] t1, t2;
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always @* begin
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casex (a)
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16'b1xxx:
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t1 <= 1;
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16'bx1xx:
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t1 <= 2;
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16'bxx1x:
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t1 <= 3;
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16'bxxx1:
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t1 <= 4;
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default:
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t1 <= 0;
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endcase
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casex (a)
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16'b1xxx:
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t2 <= 1;
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16'b01xx:
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t2 <= 2;
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16'b001x:
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t2 <= 3;
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16'b0001:
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t2 <= 4;
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default:
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t2 <= 0;
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endcase
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end
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assign y = t1 != t2;
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endmodule
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// ------------------------------------
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module example003(a_shl, a_shr, a_sshl, a_sshr, sh, y_shl, y_shr, y_sshl, y_sshr);
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input [7:0] a_shl, a_shr;
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input signed [7:0] a_sshl, a_sshr;
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input [3:0] sh;
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output [7:0] y_shl = a_shl << sh, y_shr = a_shr >> sh;
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output signed [7:0] y_sshl = a_sshl <<< sh, y_sshr = a_sshr >>> sh;
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endmodule
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// ------------------------------------
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module example004(clk, rst, y);
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input clk, rst;
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output y;
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reg [3:0] counter;
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always @(posedge clk)
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case (1'b1)
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rst, counter == 9:
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counter <= 0;
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default:
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counter <= counter+1;
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endcase
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assign y = counter == 12;
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endmodule
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