mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-03 21:09:12 +00:00
604 lines
18 KiB
C++
604 lines
18 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2018 whitequark <whitequark@whitequark.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/modtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct dlogic_t {
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IdString cell_type;
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// LUT input idx -> hard cell's port name
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dict<int, IdString> lut_input_port;
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};
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struct OptLutWorker
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{
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const std::vector<dlogic_t> &dlogic;
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RTLIL::Module *module;
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ModIndex index;
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SigMap sigmap;
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pool<RTLIL::Cell*> luts;
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dict<RTLIL::Cell*, int> luts_arity;
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dict<RTLIL::Cell*, pool<std::pair<int, RTLIL::Cell*>>> luts_dlogics;
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dict<RTLIL::Cell*, pool<int>> luts_dlogic_inputs;
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int eliminated_count = 0, combined_count = 0;
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bool evaluate_lut(RTLIL::Cell *lut, dict<SigBit, bool> inputs)
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{
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SigSpec lut_input = sigmap(lut->getPort(ID::A));
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int lut_width = lut->getParam(ID::WIDTH).as_int();
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Const lut_table = lut->getParam(ID::LUT);
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int lut_index = 0;
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for (int i = 0; i < lut_width; i++)
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{
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SigBit input = sigmap(lut_input[i]);
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if (inputs.count(input))
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{
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lut_index |= inputs[input] << i;
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}
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else
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{
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lut_index |= SigSpec(lut_input[i]).as_bool() << i;
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}
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}
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return lut_table.extract(lut_index).as_bool();
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}
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void show_stats_by_arity()
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{
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dict<int, int> arity_counts;
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std::vector<int> dlogic_counts(dlogic.size());
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int max_arity = 0;
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for (auto lut_arity : luts_arity)
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{
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max_arity = max(max_arity, lut_arity.second);
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arity_counts[lut_arity.second]++;
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}
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for (auto &lut_dlogics : luts_dlogics)
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{
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for (auto &lut_dlogic : lut_dlogics.second)
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{
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dlogic_counts[lut_dlogic.first]++;
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}
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}
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log("Number of LUTs: %8d\n", GetSize(luts));
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for (int arity = 1; arity <= max_arity; arity++)
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{
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if (arity_counts[arity])
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log(" %d-LUT %16d\n", arity, arity_counts[arity]);
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}
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for (int i = 0; i < GetSize(dlogic); i++)
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{
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log(" with %-12s (#%d) %4d\n", dlogic[i].cell_type.c_str(), i, dlogic_counts[i]);
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}
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}
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OptLutWorker(const std::vector<dlogic_t> &dlogic, RTLIL::Module *module, int limit) :
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dlogic(dlogic), module(module), index(module), sigmap(module)
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{
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log("Discovering LUTs.\n");
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for (auto cell : module->selected_cells())
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{
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if (cell->type == ID($lut))
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{
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if (cell->has_keep_attr())
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continue;
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SigBit lut_output = cell->getPort(ID::Y);
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if (lut_output.wire->get_bool_attribute(ID::keep))
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continue;
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int lut_width = cell->getParam(ID::WIDTH).as_int();
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SigSpec lut_input = cell->getPort(ID::A);
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int lut_arity = 0;
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log_debug("Found $lut\\WIDTH=%d cell %s.%s.\n", lut_width, log_id(module), log_id(cell));
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luts.insert(cell);
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// First, find all dedicated logic we're connected to. This results in an overapproximation
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// of such connections.
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pool<std::pair<int, RTLIL::Cell*>> lut_all_dlogics;
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for (int i = 0; i < lut_width; i++)
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{
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SigBit bit = lut_input[i];
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for (auto &port : index.query_ports(bit))
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{
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for (int j = 0; j < GetSize(dlogic); j++)
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{
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if (dlogic[j].cell_type == port.cell->type)
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{
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if (port.port == dlogic[j].lut_input_port.at(i, IdString()))
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{
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lut_all_dlogics.insert({j, port.cell});
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}
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}
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}
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}
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}
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// Second, make sure that the connection to dedicated logic is legal. If it is not legal,
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// it means one of the two things:
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// * The connection is spurious. I.e. this is dedicated logic that will be packed
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// with some other LUT, and it just happens to be connected to this LUT as well.
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// * The connection is illegal.
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// In either of these cases, we don't need to concern ourselves with preserving the connection
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// between this LUT and this dedicated logic cell.
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pool<std::pair<int, RTLIL::Cell*>> lut_legal_dlogics;
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pool<int> lut_dlogic_inputs;
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for (auto lut_dlogic : lut_all_dlogics)
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{
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auto &dlogic_map = dlogic[lut_dlogic.first].lut_input_port;
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bool legal = true;
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for (auto &dlogic_conn : dlogic_map)
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{
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if (lut_width <= dlogic_conn.first)
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{
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log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type.c_str(), log_id(module), log_id(lut_dlogic.second));
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log_debug(" LUT input A[%d] not present.\n", dlogic_conn.first);
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legal = false;
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break;
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}
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if (sigmap(lut_input[dlogic_conn.first]) != sigmap(lut_dlogic.second->getPort(dlogic_conn.second)))
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{
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log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type.c_str(), log_id(module), log_id(lut_dlogic.second));
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log_debug(" LUT input A[%d] (wire %s) not connected to %s port %s (wire %s).\n", dlogic_conn.first, log_signal(lut_input[dlogic_conn.first]), lut_dlogic.second->type.c_str(), dlogic_conn.second.c_str(), log_signal(lut_dlogic.second->getPort(dlogic_conn.second)));
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legal = false;
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break;
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}
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}
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if (legal)
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{
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log_debug(" LUT has legal connection to %s cell %s.%s.\n", lut_dlogic.second->type.c_str(), log_id(module), log_id(lut_dlogic.second));
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lut_legal_dlogics.insert(lut_dlogic);
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for (auto &dlogic_conn : dlogic_map)
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lut_dlogic_inputs.insert(dlogic_conn.first);
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}
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}
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// Third, determine LUT arity. An n-wide LUT that has k constant inputs and m inputs shared with dedicated
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// logic implements an (n-k-m)-ary function.
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for (int i = 0; i < lut_width; i++)
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{
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SigBit bit = lut_input[i];
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if (bit.wire || lut_dlogic_inputs.count(i))
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lut_arity++;
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}
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log_debug(" Cell implements a %d-LUT.\n", lut_arity);
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luts_arity[cell] = lut_arity;
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luts_dlogics[cell] = lut_legal_dlogics;
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luts_dlogic_inputs[cell] = lut_dlogic_inputs;
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}
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}
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show_stats_by_arity();
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log("\n");
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log("Eliminating LUTs.\n");
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pool<RTLIL::Cell*> worklist = luts;
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while (worklist.size())
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{
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if (limit == 0)
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{
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log("Limit reached.\n");
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break;
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}
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auto lut = worklist.pop();
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SigSpec lut_input = sigmap(lut->getPort(ID::A));
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pool<int> &lut_dlogic_inputs = luts_dlogic_inputs[lut];
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vector<SigBit> lut_inputs;
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for (auto &bit : lut_input)
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{
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if (bit.wire)
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lut_inputs.push_back(sigmap(bit));
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}
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bool const0_match = true;
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bool const1_match = true;
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vector<bool> input_matches;
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for (size_t i = 0; i < lut_inputs.size(); i++)
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input_matches.push_back(true);
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for (int eval = 0; eval < 1 << lut_inputs.size(); eval++)
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{
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dict<SigBit, bool> eval_inputs;
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for (size_t i = 0; i < lut_inputs.size(); i++)
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eval_inputs[lut_inputs[i]] = (eval >> i) & 1;
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bool value = evaluate_lut(lut, eval_inputs);
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if (value != 0)
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const0_match = false;
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if (value != 1)
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const1_match = false;
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for (size_t i = 0; i < lut_inputs.size(); i++)
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{
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if (value != eval_inputs[lut_inputs[i]])
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input_matches[i] = false;
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}
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}
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int input_match = -1;
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for (size_t i = 0; i < lut_inputs.size(); i++)
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if (input_matches[i])
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input_match = i;
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if (const0_match || const1_match || input_match != -1)
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{
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log_debug("Found redundant cell %s.%s.\n", log_id(module), log_id(lut));
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SigBit value;
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if (const0_match)
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{
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log_debug(" Cell evaluates constant 0.\n");
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value = State::S0;
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}
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if (const1_match)
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{
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log_debug(" Cell evaluates constant 1.\n");
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value = State::S1;
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}
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if (input_match != -1) {
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log_debug(" Cell evaluates signal %s.\n", log_signal(lut_inputs[input_match]));
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value = lut_inputs[input_match];
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}
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if (lut_dlogic_inputs.size())
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log_debug(" Not eliminating cell (connected to dedicated logic).\n");
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else
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{
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SigSpec lut_output = lut->getPort(ID::Y);
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for (auto &port : index.query_ports(lut_output))
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{
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if (port.cell != lut && luts.count(port.cell))
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worklist.insert(port.cell);
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}
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module->connect(lut_output, value);
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sigmap.add(lut_output, value);
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luts.erase(lut);
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luts_arity.erase(lut);
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luts_dlogics.erase(lut);
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luts_dlogic_inputs.erase(lut);
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module->remove(lut);
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eliminated_count++;
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if (limit > 0)
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limit--;
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}
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}
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}
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show_stats_by_arity();
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log("\n");
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log("Combining LUTs.\n");
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worklist = luts;
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while (worklist.size())
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{
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if (limit == 0)
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{
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log("Limit reached.\n");
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break;
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}
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auto lutA = worklist.pop();
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SigSpec lutA_input = sigmap(lutA->getPort(ID::A));
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SigSpec lutA_output = sigmap(lutA->getPort(ID::Y)[0]);
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int lutA_width = lutA->getParam(ID::WIDTH).as_int();
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int lutA_arity = luts_arity[lutA];
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pool<int> &lutA_dlogic_inputs = luts_dlogic_inputs[lutA];
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auto lutA_output_ports = index.query_ports(lutA->getPort(ID::Y));
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if (lutA_output_ports.size() != 2)
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continue;
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for (auto &port : lutA_output_ports)
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{
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if (port.cell == lutA)
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continue;
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if (luts.count(port.cell))
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{
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auto lutB = port.cell;
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SigSpec lutB_input = sigmap(lutB->getPort(ID::A));
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SigSpec lutB_output = sigmap(lutB->getPort(ID::Y)[0]);
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int lutB_width = lutB->getParam(ID::WIDTH).as_int();
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int lutB_arity = luts_arity[lutB];
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pool<int> &lutB_dlogic_inputs = luts_dlogic_inputs[lutB];
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log_debug("Found %s.%s (cell A) feeding %s.%s (cell B).\n", log_id(module), log_id(lutA), log_id(module), log_id(lutB));
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if (index.query_is_output(lutA->getPort(ID::Y)))
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{
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log_debug(" Not combining LUTs (cascade connection feeds module output).\n");
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continue;
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}
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pool<SigBit> lutA_inputs;
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pool<SigBit> lutB_inputs;
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for (auto &bit : lutA_input)
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{
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if (bit.wire)
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lutA_inputs.insert(sigmap(bit));
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}
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for (auto &bit : lutB_input)
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{
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if (bit.wire)
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lutB_inputs.insert(sigmap(bit));
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}
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pool<SigBit> common_inputs;
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for (auto &bit : lutA_inputs)
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{
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if (lutB_inputs.count(bit))
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common_inputs.insert(bit);
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}
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int lutM_arity = lutA_arity + lutB_arity - 1 - common_inputs.size();
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if (lutA_dlogic_inputs.size())
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log_debug(" Cell A is a %d-LUT with %d dedicated connections. ", lutA_arity, GetSize(lutA_dlogic_inputs));
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else
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log_debug(" Cell A is a %d-LUT. ", lutA_arity);
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if (lutB_dlogic_inputs.size())
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log_debug("Cell B is a %d-LUT with %d dedicated connections.\n", lutB_arity, GetSize(lutB_dlogic_inputs));
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else
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log_debug("Cell B is a %d-LUT.\n", lutB_arity);
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log_debug(" Cells share %d input(s) and can be merged into one %d-LUT.\n", GetSize(common_inputs), lutM_arity);
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const int COMBINE_A = 1, COMBINE_B = 2, COMBINE_EITHER = COMBINE_A | COMBINE_B;
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int combine_mask = 0;
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if (lutM_arity > lutA_width)
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log_debug(" Not combining LUTs into cell A (combined LUT wider than cell A).\n");
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else if (lutB_dlogic_inputs.size() > 0)
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log_debug(" Not combining LUTs into cell A (cell B is connected to dedicated logic).\n");
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else if (lutB->get_bool_attribute(ID::lut_keep))
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log_debug(" Not combining LUTs into cell A (cell B has attribute \\lut_keep).\n");
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else
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combine_mask |= COMBINE_A;
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if (lutM_arity > lutB_width)
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log_debug(" Not combining LUTs into cell B (combined LUT wider than cell B).\n");
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else if (lutA_dlogic_inputs.size() > 0)
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log_debug(" Not combining LUTs into cell B (cell A is connected to dedicated logic).\n");
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else if (lutA->get_bool_attribute(ID::lut_keep))
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log_debug(" Not combining LUTs into cell B (cell A has attribute \\lut_keep).\n");
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else
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combine_mask |= COMBINE_B;
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int combine = combine_mask;
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if (combine == COMBINE_EITHER)
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{
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log_debug(" Can combine into either cell.\n");
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if (lutA_arity == 1)
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{
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log_debug(" Cell A is a buffer or inverter, combining into cell B.\n");
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combine = COMBINE_B;
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}
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else if (lutB_arity == 1)
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{
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log_debug(" Cell B is a buffer or inverter, combining into cell A.\n");
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combine = COMBINE_A;
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}
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else
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{
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log_debug(" Arbitrarily combining into cell A.\n");
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combine = COMBINE_A;
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}
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}
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RTLIL::Cell *lutM, *lutR;
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pool<SigBit> lutM_inputs, lutR_inputs;
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pool<int> lutM_dlogic_inputs;
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if (combine == COMBINE_A)
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{
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log_debug(" Combining LUTs into cell A.\n");
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lutM = lutA;
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lutM_inputs = lutA_inputs;
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lutM_dlogic_inputs = lutA_dlogic_inputs;
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lutR = lutB;
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lutR_inputs = lutB_inputs;
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}
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else if (combine == COMBINE_B)
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{
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log_debug(" Combining LUTs into cell B.\n");
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lutM = lutB;
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lutM_inputs = lutB_inputs;
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lutM_dlogic_inputs = lutB_dlogic_inputs;
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lutR = lutA;
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lutR_inputs = lutA_inputs;
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}
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else
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{
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log_debug(" Cannot combine LUTs.\n");
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continue;
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}
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pool<SigBit> lutR_unique;
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for (auto &bit : lutR_inputs)
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{
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if (!common_inputs.count(bit) && bit != lutA_output)
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lutR_unique.insert(bit);
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}
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int lutM_width = lutM->getParam(ID::WIDTH).as_int();
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SigSpec lutM_input = sigmap(lutM->getPort(ID::A));
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std::vector<SigBit> lutM_new_inputs;
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for (int i = 0; i < lutM_width; i++)
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{
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bool input_unused = false;
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if (sigmap(lutM_input[i]) == lutA_output)
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input_unused = true;
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if (!lutM_input[i].wire && !lutM_dlogic_inputs.count(i))
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input_unused = true;
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if (input_unused && lutR_unique.size())
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{
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SigBit new_input = lutR_unique.pop();
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log_debug(" Connecting input %d as %s.\n", i, log_signal(new_input));
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lutM_new_inputs.push_back(new_input);
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}
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else if (sigmap(lutM_input[i]) == lutA_output)
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{
|
|
log_debug(" Disconnecting cascade input %d.\n", i);
|
|
lutM_new_inputs.push_back(SigBit());
|
|
}
|
|
else
|
|
{
|
|
log_debug(" Leaving input %d as %s.\n", i, log_signal(lutM_input[i]));
|
|
lutM_new_inputs.push_back(lutM_input[i]);
|
|
}
|
|
}
|
|
log_assert(lutR_unique.size() == 0);
|
|
|
|
RTLIL::Const lutM_new_table(State::Sx, 1 << lutM_width);
|
|
for (int eval = 0; eval < 1 << lutM_width; eval++)
|
|
{
|
|
dict<SigBit, bool> eval_inputs;
|
|
for (size_t i = 0; i < lutM_new_inputs.size(); i++)
|
|
{
|
|
eval_inputs[lutM_new_inputs[i]] = (eval >> i) & 1;
|
|
}
|
|
eval_inputs[lutA_output] = evaluate_lut(lutA, eval_inputs);
|
|
lutM_new_table[eval] = (RTLIL::State) evaluate_lut(lutB, eval_inputs);
|
|
}
|
|
|
|
log_debug(" Cell A truth table: %s.\n", lutA->getParam(ID::LUT).as_string().c_str());
|
|
log_debug(" Cell B truth table: %s.\n", lutB->getParam(ID::LUT).as_string().c_str());
|
|
log_debug(" Merged truth table: %s.\n", lutM_new_table.as_string().c_str());
|
|
|
|
lutM->setParam(ID::LUT, lutM_new_table);
|
|
lutM->setPort(ID::A, lutM_new_inputs);
|
|
lutM->setPort(ID::Y, lutB_output);
|
|
|
|
luts_arity[lutM] = lutM_arity;
|
|
luts.erase(lutR);
|
|
luts_arity.erase(lutR);
|
|
|
|
worklist.insert(lutM);
|
|
worklist.erase(lutR);
|
|
|
|
lutR->module->remove(lutR);
|
|
|
|
combined_count++;
|
|
if (limit > 0)
|
|
limit--;
|
|
}
|
|
}
|
|
}
|
|
show_stats_by_arity();
|
|
}
|
|
};
|
|
|
|
static void split(std::vector<std::string> &tokens, const std::string &text, char sep)
|
|
{
|
|
size_t start = 0, end = 0;
|
|
while ((end = text.find(sep, start)) != std::string::npos) {
|
|
tokens.push_back(text.substr(start, end - start));
|
|
start = end + 1;
|
|
}
|
|
tokens.push_back(text.substr(start));
|
|
}
|
|
|
|
struct OptLutPass : public Pass {
|
|
OptLutPass() : Pass("opt_lut", "optimize LUT cells") { }
|
|
void help() override
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" opt_lut [options] [selection]\n");
|
|
log("\n");
|
|
log("This pass combines cascaded $lut cells with unused inputs.\n");
|
|
log("\n");
|
|
log(" -dlogic <type>:<cell-port>=<LUT-input>[:<cell-port>=<LUT-input>...]\n");
|
|
log(" preserve connections to dedicated logic cell <type> that has ports\n");
|
|
log(" <cell-port> connected to LUT inputs <LUT-input>. this includes\n");
|
|
log(" the case where both LUT and dedicated logic input are connected to\n");
|
|
log(" the same constant.\n");
|
|
log("\n");
|
|
log(" -limit N\n");
|
|
log(" only perform the first N combines, then stop. useful for debugging.\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
|
{
|
|
log_header(design, "Executing OPT_LUT pass (optimize LUTs).\n");
|
|
|
|
std::vector<dlogic_t> dlogic;
|
|
int limit = -1;
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++)
|
|
{
|
|
if (args[argidx] == "-dlogic" && argidx+1 < args.size())
|
|
{
|
|
std::vector<std::string> tokens;
|
|
split(tokens, args[++argidx], ':');
|
|
if (tokens.size() < 2)
|
|
log_cmd_error("The -dlogic option requires at least one connection.\n");
|
|
dlogic_t entry;
|
|
entry.cell_type = "\\" + tokens[0];
|
|
for (auto it = tokens.begin() + 1; it != tokens.end(); ++it) {
|
|
std::vector<std::string> conn_tokens;
|
|
split(conn_tokens, *it, '=');
|
|
if (conn_tokens.size() != 2)
|
|
log_cmd_error("Invalid format of -dlogic signal mapping.\n");
|
|
IdString logic_port = "\\" + conn_tokens[0];
|
|
int lut_input = atoi(conn_tokens[1].c_str());
|
|
entry.lut_input_port[lut_input] = logic_port;
|
|
}
|
|
dlogic.push_back(entry);
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-limit" && argidx + 1 < args.size())
|
|
{
|
|
limit = atoi(args[++argidx].c_str());
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(args, argidx, design);
|
|
|
|
int eliminated_count = 0, combined_count = 0;
|
|
for (auto module : design->selected_modules())
|
|
{
|
|
OptLutWorker worker(dlogic, module, limit - eliminated_count - combined_count);
|
|
eliminated_count += worker.eliminated_count;
|
|
combined_count += worker.combined_count;
|
|
}
|
|
if (eliminated_count)
|
|
design->scratchpad_set_bool("opt.did_something", true);
|
|
if (combined_count)
|
|
design->scratchpad_set_bool("opt.did_something", true);
|
|
log("\n");
|
|
log("Eliminated %d LUTs.\n", eliminated_count);
|
|
log("Combined %d LUTs.\n", combined_count);
|
|
}
|
|
} OptLutPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|