mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-03 21:09:12 +00:00
584 lines
17 KiB
C++
584 lines
17 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2018 whitequark <whitequark@whitequark.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "backends/rtlil/rtlil_backend.h"
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USING_YOSYS_NAMESPACE
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using namespace RTLIL_BACKEND;
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PRIVATE_NAMESPACE_BEGIN
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struct BugpointPass : public Pass {
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BugpointPass() : Pass("bugpoint", "minimize testcases") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" bugpoint [options] [-script <filename> | -command \"<command>\"]\n");
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log("\n");
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log("This command minimizes the current design that is known to crash Yosys with the\n");
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log("given script into a smaller testcase. It does this by removing an arbitrary part\n");
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log("of the design and recursively invokes a new Yosys process with this modified design\n");
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log("and the same script, repeating these steps while it can find a smaller design that\n");
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log("still causes a crash. Once this command finishes, it replaces the current design\n");
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log("with the smallest testcase it was able to produce.\n");
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log("In order to save the reduced testcase you must write this out to a file with\n");
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log("another command after `bugpoint` like `write_rtlil` or `write_verilog`.\n");
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log("\n");
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log(" -script <filename> | -command \"<command>\"\n");
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log(" use this script file or command to crash Yosys. required.\n");
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log("\n");
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log(" -yosys <filename>\n");
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log(" use this Yosys binary. if not specified, `yosys` is used.\n");
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log("\n");
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log(" -grep \"<string>\"\n");
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log(" only consider crashes that place this string in the log file.\n");
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log("\n");
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log(" -fast\n");
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log(" run `proc_clean; clean -purge` after each minimization step. converges\n");
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log(" faster, but produces larger testcases, and may fail to produce any\n");
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log(" testcase at all if the crash is related to dangling wires.\n");
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log("\n");
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log(" -clean\n");
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log(" run `proc_clean; clean -purge` before checking testcase and after\n");
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log(" finishing. produces smaller and more useful testcases, but may fail to\n");
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log(" produce any testcase at all if the crash is related to dangling wires.\n");
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log("\n");
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log("It is possible to constrain which parts of the design will be considered for\n");
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log("removal. Unless one or more of the following options are specified, all parts\n");
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log("will be considered.\n");
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log("\n");
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log(" -modules\n");
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log(" try to remove modules. modules with a (* bugpoint_keep *) attribute\n");
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log(" will be skipped.\n");
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log("\n");
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log(" -ports\n");
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log(" try to remove module ports. ports with a (* bugpoint_keep *) attribute\n");
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log(" will be skipped (useful for clocks, resets, etc.)\n");
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log("\n");
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log(" -cells\n");
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log(" try to remove cells. cells with a (* bugpoint_keep *) attribute will\n");
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log(" be skipped.\n");
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log("\n");
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log(" -connections\n");
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log(" try to reconnect ports to 'x.\n");
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log("\n");
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log(" -processes\n");
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log(" try to remove processes. processes with a (* bugpoint_keep *) attribute\n");
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log(" will be skipped.\n");
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log("\n");
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log(" -assigns\n");
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log(" try to remove process assigns from cases.\n");
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log("\n");
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log(" -updates\n");
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log(" try to remove process updates from syncs.\n");
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log("\n");
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log(" -runner \"<prefix>\"\n");
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log(" child process wrapping command, e.g., \"timeout 30\", or valgrind.\n");
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log("\n");
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}
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bool run_yosys(RTLIL::Design *design, string runner, string yosys_cmd, string yosys_arg)
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{
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design->sort();
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std::ofstream f("bugpoint-case.il");
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RTLIL_BACKEND::dump_design(f, design, /*only_selected=*/false, /*flag_m=*/true, /*flag_n=*/false);
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f.close();
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string yosys_cmdline = stringf("%s %s -qq -L bugpoint-case.log %s bugpoint-case.il", runner.c_str(), yosys_cmd.c_str(), yosys_arg.c_str());
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return run_command(yosys_cmdline) == 0;
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}
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bool check_logfile(string grep)
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{
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if (grep.empty())
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return true;
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if (grep.size() > 2 && grep.front() == '"' && grep.back() == '"')
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grep = grep.substr(1, grep.size() - 2);
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std::ifstream f("bugpoint-case.log");
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while (!f.eof())
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{
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string line;
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getline(f, line);
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if (line.find(grep) != std::string::npos)
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return true;
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}
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return false;
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}
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RTLIL::Design *clean_design(RTLIL::Design *design, bool do_clean = true, bool do_delete = false)
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{
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if (!do_clean)
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return design;
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RTLIL::Design *design_copy = new RTLIL::Design;
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for (auto module : design->modules())
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design_copy->add(module->clone());
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Pass::call(design_copy, "proc_clean -quiet");
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Pass::call(design_copy, "clean -purge");
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if (do_delete)
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delete design;
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return design_copy;
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}
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RTLIL::Design *simplify_something(RTLIL::Design *design, int &seed, bool stage2, bool modules, bool ports, bool cells, bool connections, bool processes, bool assigns, bool updates, bool wires)
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{
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RTLIL::Design *design_copy = new RTLIL::Design;
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for (auto module : design->modules())
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design_copy->add(module->clone());
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int index = 0;
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if (modules)
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{
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Module *removed_module = nullptr;
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for (auto module : design_copy->modules())
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{
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if (module->get_blackbox_attribute())
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continue;
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if (module->get_bool_attribute(ID::bugpoint_keep))
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continue;
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if (index++ == seed)
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{
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log_header(design, "Trying to remove module %s.\n", log_id(module));
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removed_module = module;
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break;
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}
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}
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if (removed_module) {
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design_copy->remove(removed_module);
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return design_copy;
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}
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}
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if (ports)
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{
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for (auto mod : design_copy->modules())
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{
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if (mod->get_blackbox_attribute())
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continue;
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for (auto wire : mod->wires())
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{
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if (!wire->port_id)
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continue;
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if (!stage2 && wire->get_bool_attribute(ID($bugpoint)))
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continue;
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if (wire->get_bool_attribute(ID::bugpoint_keep))
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continue;
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if (index++ == seed)
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{
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log_header(design, "Trying to remove module port %s.\n", log_id(wire));
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wire->port_input = wire->port_output = false;
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mod->fixup_ports();
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return design_copy;
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}
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}
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}
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}
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if (cells)
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{
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for (auto mod : design_copy->modules())
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{
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if (mod->get_blackbox_attribute())
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continue;
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Cell *removed_cell = nullptr;
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for (auto cell : mod->cells())
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{
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if (cell->get_bool_attribute(ID::bugpoint_keep))
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continue;
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if (index++ == seed)
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{
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log_header(design, "Trying to remove cell %s.%s.\n", log_id(mod), log_id(cell));
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removed_cell = cell;
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break;
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}
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}
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if (removed_cell) {
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mod->remove(removed_cell);
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return design_copy;
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}
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}
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}
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if (connections)
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{
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for (auto mod : design_copy->modules())
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{
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if (mod->get_blackbox_attribute())
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continue;
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for (auto cell : mod->cells())
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{
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for (auto it : cell->connections_)
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{
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RTLIL::SigSpec port = cell->getPort(it.first);
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bool is_undef = port.is_fully_undef();
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bool is_port = port.is_wire() && (port.as_wire()->port_input || port.as_wire()->port_output);
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if(is_undef || (!stage2 && is_port))
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continue;
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if (index++ == seed)
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{
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log_header(design, "Trying to remove cell port %s.%s.%s.\n", log_id(mod), log_id(cell), log_id(it.first));
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RTLIL::SigSpec port_x(State::Sx, port.size());
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cell->unsetPort(it.first);
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cell->setPort(it.first, port_x);
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return design_copy;
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}
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if (!stage2 && (cell->input(it.first) || cell->output(it.first)) && index++ == seed)
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{
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log_header(design, "Trying to expose cell port %s.%s.%s as module port.\n", log_id(mod), log_id(cell), log_id(it.first));
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RTLIL::Wire *wire = mod->addWire(NEW_ID, port.size());
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wire->set_bool_attribute(ID($bugpoint));
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wire->port_input = cell->input(it.first);
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wire->port_output = cell->output(it.first);
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cell->unsetPort(it.first);
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cell->setPort(it.first, wire);
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mod->fixup_ports();
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return design_copy;
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}
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}
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}
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}
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}
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if (processes)
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{
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for (auto mod : design_copy->modules())
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{
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if (mod->get_blackbox_attribute())
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continue;
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RTLIL::Process *removed_process = nullptr;
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for (auto process : mod->processes)
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{
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if (process.second->get_bool_attribute(ID::bugpoint_keep))
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continue;
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if (index++ == seed)
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{
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log_header(design, "Trying to remove process %s.%s.\n", log_id(mod), log_id(process.first));
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removed_process = process.second;
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break;
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}
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}
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if (removed_process) {
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mod->remove(removed_process);
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return design_copy;
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}
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}
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}
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if (assigns)
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{
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for (auto mod : design_copy->modules())
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{
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if (mod->get_blackbox_attribute())
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continue;
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for (auto &pr : mod->processes)
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{
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vector<RTLIL::CaseRule*> cases = {&pr.second->root_case};
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while (!cases.empty())
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{
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RTLIL::CaseRule *cs = cases[0];
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cases.erase(cases.begin());
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for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it)
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{
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if (index++ == seed)
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{
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log_header(design, "Trying to remove assign %s %s in %s.%s.\n", log_signal(it->first), log_signal(it->second), log_id(mod), log_id(pr.first));
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cs->actions.erase(it);
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return design_copy;
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}
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}
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for (auto &sw : cs->switches)
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cases.insert(cases.end(), sw->cases.begin(), sw->cases.end());
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}
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}
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}
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}
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if (updates)
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{
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for (auto mod : design_copy->modules())
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{
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if (mod->get_blackbox_attribute())
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continue;
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for (auto &pr : mod->processes)
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{
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for (auto &sy : pr.second->syncs)
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{
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for (auto it = sy->actions.begin(); it != sy->actions.end(); ++it)
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{
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if (index++ == seed)
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{
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log_header(design, "Trying to remove sync %s update %s %s in %s.%s.\n", log_signal(sy->signal), log_signal(it->first), log_signal(it->second), log_id(mod), log_id(pr.first));
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sy->actions.erase(it);
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return design_copy;
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}
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}
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int i = 0;
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for (auto it = sy->mem_write_actions.begin(); it != sy->mem_write_actions.end(); ++it, ++i)
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{
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if (index++ == seed)
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{
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log_header(design, "Trying to remove sync %s memwr %s %s %s %s in %s.%s.\n", log_signal(sy->signal), log_id(it->memid), log_signal(it->address), log_signal(it->data), log_signal(it->enable), log_id(mod), log_id(pr.first));
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sy->mem_write_actions.erase(it);
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// Remove the bit for removed action from other actions' priority masks.
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for (auto it2 = sy->mem_write_actions.begin(); it2 != sy->mem_write_actions.end(); ++it2) {
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auto &mask = it2->priority_mask;
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if (GetSize(mask) > i) {
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mask.bits.erase(mask.bits.begin() + i);
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}
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}
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return design_copy;
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}
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}
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}
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}
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}
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}
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if (wires)
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{
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for (auto mod : design_copy->modules())
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{
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if (mod->get_blackbox_attribute())
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continue;
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Wire *removed_wire = nullptr;
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for (auto wire : mod->wires())
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{
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if (wire->get_bool_attribute(ID::bugpoint_keep))
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continue;
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if (wire->name.begins_with("$delete_wire") || wire->name.begins_with("$auto$bugpoint"))
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continue;
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if (index++ == seed)
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{
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log_header(design, "Trying to remove wire %s.%s.\n", log_id(mod), log_id(wire));
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removed_wire = wire;
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break;
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}
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}
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if (removed_wire) {
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mod->remove({removed_wire});
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return design_copy;
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}
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}
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}
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return nullptr;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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string yosys_cmd = "yosys", yosys_arg, grep, runner;
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bool fast = false, clean = false;
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bool modules = false, ports = false, cells = false, connections = false, processes = false, assigns = false, updates = false, wires = false, has_part = false;
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log_header(design, "Executing BUGPOINT pass (minimize testcases).\n");
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log_push();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-yosys" && argidx + 1 < args.size()) {
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yosys_cmd = args[++argidx];
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continue;
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}
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if (args[argidx] == "-script" && argidx + 1 < args.size()) {
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if (!yosys_arg.empty())
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log_cmd_error("A -script or -command option can be only provided once!\n");
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yosys_arg = stringf("-s %s", args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-command" && argidx + 1 < args.size()) {
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if (!yosys_arg.empty())
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log_cmd_error("A -script or -command option can be only provided once!\n");
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yosys_arg = stringf("-p %s", args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-grep" && argidx + 1 < args.size()) {
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grep = args[++argidx];
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continue;
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}
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if (args[argidx] == "-fast") {
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fast = true;
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continue;
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}
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if (args[argidx] == "-clean") {
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clean = true;
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continue;
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}
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if (args[argidx] == "-modules") {
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modules = true;
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has_part = true;
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continue;
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}
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if (args[argidx] == "-ports") {
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ports = true;
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has_part = true;
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continue;
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}
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if (args[argidx] == "-cells") {
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cells = true;
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has_part = true;
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continue;
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}
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if (args[argidx] == "-connections") {
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connections = true;
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has_part = true;
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continue;
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}
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if (args[argidx] == "-processes") {
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processes = true;
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has_part = true;
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continue;
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}
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if (args[argidx] == "-assigns") {
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assigns = true;
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has_part = true;
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continue;
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}
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if (args[argidx] == "-updates") {
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updates = true;
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has_part = true;
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continue;
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}
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if (args[argidx] == "-wires") {
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wires = true;
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has_part = true;
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continue;
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}
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if (args[argidx] == "-runner" && argidx + 1 < args.size()) {
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runner = args[++argidx];
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if (runner.size() && runner.at(0) == '"') {
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log_assert(runner.back() == '"');
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runner = runner.substr(1, runner.size() - 2);
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}
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (yosys_arg.empty())
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log_cmd_error("Missing -script or -command option.\n");
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if (!has_part)
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{
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modules = true;
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ports = true;
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cells = true;
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connections = true;
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processes = true;
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assigns = true;
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updates = true;
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wires = true;
|
|
}
|
|
|
|
if (!design->full_selection())
|
|
log_cmd_error("This command only operates on fully selected designs!\n");
|
|
|
|
RTLIL::Design *crashing_design = clean_design(design, clean);
|
|
if (run_yosys(crashing_design, runner, yosys_cmd, yosys_arg))
|
|
log_cmd_error("The provided script file or command and Yosys binary do not crash on this design!\n");
|
|
if (!check_logfile(grep))
|
|
log_cmd_error("The provided grep string is not found in the log file!\n");
|
|
|
|
int seed = 0;
|
|
bool found_something = false, stage2 = false;
|
|
while (true)
|
|
{
|
|
if (RTLIL::Design *simplified = simplify_something(crashing_design, seed, stage2, modules, ports, cells, connections, processes, assigns, updates, wires))
|
|
{
|
|
simplified = clean_design(simplified, fast, /*do_delete=*/true);
|
|
|
|
bool crashes;
|
|
if (clean)
|
|
{
|
|
RTLIL::Design *testcase = clean_design(simplified);
|
|
crashes = !run_yosys(testcase, runner, yosys_cmd, yosys_arg);
|
|
delete testcase;
|
|
}
|
|
else
|
|
{
|
|
crashes = !run_yosys(simplified, runner, yosys_cmd, yosys_arg);
|
|
}
|
|
|
|
if (crashes && check_logfile(grep))
|
|
{
|
|
log("Testcase crashes.\n");
|
|
if (crashing_design != design)
|
|
delete crashing_design;
|
|
crashing_design = simplified;
|
|
found_something = true;
|
|
}
|
|
else
|
|
{
|
|
log("Testcase does not crash.\n");
|
|
delete simplified;
|
|
seed++;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
seed = 0;
|
|
if (found_something)
|
|
found_something = false;
|
|
else
|
|
{
|
|
if (!stage2)
|
|
{
|
|
log("Demoting introduced module ports.\n");
|
|
stage2 = true;
|
|
}
|
|
else
|
|
{
|
|
log("Simplifications exhausted.\n");
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (crashing_design != design)
|
|
{
|
|
Pass::call(design, "design -reset");
|
|
crashing_design = clean_design(crashing_design, clean, /*do_delete=*/true);
|
|
for (auto module : crashing_design->modules())
|
|
design->add(module->clone());
|
|
delete crashing_design;
|
|
}
|
|
|
|
log_pop();
|
|
}
|
|
} BugpointPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|