mirror of
https://github.com/YosysHQ/yosys
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25 lines
1.5 KiB
Makefile
25 lines
1.5 KiB
Makefile
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OBJS += techlibs/intel_le/synth_intel_le.o
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# Techmap
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/abc9_map.v))
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/abc9_unmap.v))
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/abc9_model.v))
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/le_map.v))
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/le_sim.v))
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/arith_le_map.v))
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/dff_map.v))
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/dff_sim.v))
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/dsp_sim.v))
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/dsp_map.v))
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/mem_sim.v))
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$(eval $(call add_share_file,share/intel_le/cycloneiv,techlibs/intel_le/cycloneiv/cells_sim.v))
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# RAM
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/bram_m9k.txt))
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/bram_m20k_map.v))
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# Miscellaneous
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/megafunction_bb.v))
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$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/quartus_rename.v))
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