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41ed6ca7a5
yosys
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techlibs
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Eddie Hung
a73f96594f
Merge pull request
#1574
from YosysHQ/eddie/xilinx_lutram
...
xilinx: add LUTRAM rules for RAM32M, RAM64M
2019-12-16 21:48:21 -08:00
..
achronix
anlogic
common
coolrunner2
coolrunner2: remove spurious log_pop() call,
fixes
#1463
2019-11-23 06:21:40 +01:00
easic
ecp5
Fix bitwidth mismatch; suppresses iverilog warning
2019-12-11 13:02:07 -08:00
efinix
gowin
Use -match-init to not synth contradicting init values
2019-12-03 15:12:25 +01:00
greenpak4
ice40
ice40_opt to restore attributes/name when unwrapping
2019-12-09 14:29:29 -08:00
intel
synth_intel: a10gx -> arria10gx
2019-12-10 13:48:10 +00:00
sf2
xilinx
Merge pull request
#1574
from YosysHQ/eddie/xilinx_lutram
2019-12-16 21:48:21 -08:00
.gitignore