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35 lines
621 B
Verilog
35 lines
621 B
Verilog
module myram(
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input rd_clk,
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input [ 7:0] rd_addr,
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output reg [17:0] rd_data,
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input wr_clk,
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input wr_enable,
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input [ 7:0] wr_addr,
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input [17:0] wr_data
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);
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reg [17:0] memory [0:255];
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integer i;
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function [17:0] hash(input [7:0] k);
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reg [31:0] x;
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begin
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x = {k, ~k, k, ~k};
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x = x ^ (x << 13);
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x = x ^ (x >> 17);
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x = x ^ (x << 5);
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hash = x;
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end
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endfunction
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initial begin
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for (i = 0; i < 256; i = i+1)
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memory[i] = hash(i);
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end
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always @(posedge rd_clk)
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rd_data <= memory[rd_addr];
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always @(posedge wr_clk)
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if (wr_enable)
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memory[wr_addr] <= wr_data;
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endmodule
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