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yosys/techlibs/intel/max10
History
Richard Herveille 2893938355 Removed SystemVerilog module end label
2024-03-19 01:31:36 +01:00
..
cells_arith.v
cells_map.v
cells_sim.v Removed SystemVerilog module end label 2024-03-19 01:31:36 +01:00
dsp_map.v