mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
21 lines
250 B
Verilog
21 lines
250 B
Verilog
module ifdef_2_top(o1, o2, o3);
|
|
|
|
output wire o1;
|
|
|
|
`define COND_1
|
|
`define COND_2
|
|
`define COND_3
|
|
|
|
`ifdef COND_1
|
|
output wire o2;
|
|
`elsif COND_2
|
|
input wire dne1;
|
|
`elsif COND_3
|
|
input wire dne2;
|
|
`else
|
|
input wire dne3;
|
|
`endif
|
|
|
|
output wire o3;
|
|
|
|
endmodule
|