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yosys/techlibs/gowin
2024-11-26 15:42:22 +01:00
..
arith_map.v
brams.txt
brams_map.v gowin: Fix SDP write enable port. 2024-01-30 17:06:59 +10:00
cells_map.v
cells_sim.v Gowin. Add the EMCU primitive. 2024-09-11 10:18:51 +10:00
cells_xtra.py gowin: split cells_xtra by family 2024-11-26 15:42:22 +01:00
cells_xtra_gw1n.v gowin: split cells_xtra by family 2024-11-26 15:42:22 +01:00
cells_xtra_gw2a.v gowin: split cells_xtra by family 2024-11-26 15:42:22 +01:00
cells_xtra_gw5a.v gowin: split cells_xtra by family 2024-11-26 15:42:22 +01:00
lutrams.txt
lutrams_map.v
Makefile.inc gowin: split cells_xtra by family 2024-11-26 15:42:22 +01:00
synth_gowin.cc gowin: split cells_xtra by family 2024-11-26 15:42:22 +01:00