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Code Activity
yosys/techlibs/xilinx
History
Krystine Sherwin 0ec5f1b756
pmgen: Move passes out of pmgen folder 
- Techlib pmgens are now in relevant techlibs/*.
- `peepopt` pmgens are now in passes/opt.
- `test_pmgen` is still in passes/pmgen.
- Update `Makefile.inc` and `.gitignore` file(s) to match new `*_pm.h` location,
  as well as the `#include`s.
- Change default `%_pm.h` make target to `techlibs/%_pm.h` and move it to the
  top level Makefile.
- Update pmgen target to use `$(notdir $*)` (where `$*` is the part of the file
  name that matched the '%' in the target) instead of `$(subst _pm.h,,$(notdir
  $@))`.
2025-01-31 15:18:28 +13:00
..
tests tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
abc9_model.v Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
arith_map.v Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
brams_defs.vh xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_xc2v.txt xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_xc2v_map.v xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_xc3sda.txt xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_xc3sda_map.v xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_xc4v.txt xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_xc4v_map.v xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_xc5v_map.v xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_xc6v_map.v xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_xcu_map.v xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_xcv.txt xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_xcv_map.v xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
cells_map.v iopadmap: Add native support for negative-polarity output enable. 2021-11-09 15:40:16 +01:00
cells_sim.v Update Xilinx cell definitions, fixes #3699 2023-03-23 09:44:36 +01:00
cells_xtra.py Update Xilinx cell definitions, fixes #3699 2023-03-23 09:44:36 +01:00
cells_xtra.v Update Xilinx cell definitions, fixes #3699 2023-03-23 09:44:36 +01:00
ff_map.v Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
lut_map.v Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
lutrams_xc5v.txt xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
lutrams_xc5v_map.v xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
lutrams_xcu.txt xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
lutrams_xcv.txt xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
lutrams_xcv_map.v xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Makefile.inc pmgen: Move passes out of pmgen folder 2025-01-31 15:18:28 +13:00
mux_map.v Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
synth_xilinx.cc synth_xilinx: add -json 2024-10-09 19:24:32 +02:00
urams.txt xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
urams_map.v xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
xc3s_mult_map.v xilinx: Support multiplier mapping for all families. 2019-10-22 18:06:57 +02:00
xc3sda_dsp_map.v xilinx_dsp: Initial DSP48A/DSP48A1 support. 2019-12-22 20:51:14 +01:00
xc4v_dsp_map.v xilinx: Support multiplier mapping for all families. 2019-10-22 18:06:57 +02:00
xc5v_dsp_map.v xilinx: Support multiplier mapping for all families. 2019-10-22 18:06:57 +02:00
xc6s_dsp_map.v xilinx_dsp: Initial DSP48A/DSP48A1 support. 2019-12-22 20:51:14 +01:00
xc7_dsp_map.v xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325) 2020-09-23 09:15:24 -07:00
xcu_dsp_map.v xilinx: Support multiplier mapping for all families. 2019-10-22 18:06:57 +02:00
xilinx_dffopt.cc rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
xilinx_dsp.cc pmgen: Move passes out of pmgen folder 2025-01-31 15:18:28 +13:00
xilinx_dsp.pmg pmgen: Move passes out of pmgen folder 2025-01-31 15:18:28 +13:00
xilinx_dsp48a.pmg pmgen: Move passes out of pmgen folder 2025-01-31 15:18:28 +13:00
xilinx_dsp_cascade.pmg pmgen: Move passes out of pmgen folder 2025-01-31 15:18:28 +13:00
xilinx_dsp_CREG.pmg pmgen: Move passes out of pmgen folder 2025-01-31 15:18:28 +13:00
xilinx_srl.cc pmgen: Move passes out of pmgen folder 2025-01-31 15:18:28 +13:00
xilinx_srl.pmg pmgen: Move passes out of pmgen folder 2025-01-31 15:18:28 +13:00