mirror of
https://github.com/YosysHQ/yosys
synced 2026-05-31 22:27:50 +00:00
252 lines
7.1 KiB
C++
252 lines
7.1 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* Copyright (C) 2018 Ruben Undheim <ruben.undheim@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys_common.h"
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#include "passes/hierarchy/util/ports.h"
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#include "kernel/sigtools.h"
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YOSYS_NAMESPACE_BEGIN
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namespace Hierarchy {
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enum class SigDirection {
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UNKNOWN,
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INPUT,
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OUTPUT,
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INOUT,
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DRIVEN
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};
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static void build_driven_signals_index(Module *module, SigMap &sigmap, SigPool &driven_signals) {
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for (auto cell : module->cells()) {
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for (auto &conn : cell->connections()) {
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if (cell->output(conn.first)) {
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SigSpec sig = sigmap(conn.second);
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driven_signals.add(sig);
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}
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}
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}
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for (auto &conn : module->connections()) {
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if (conn.second.is_fully_const()) {
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SigSpec lhs = sigmap(conn.first);
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driven_signals.add(lhs);
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}
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}
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}
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static SigDirection get_signal_direction(const SigSpec &sig, SigMap &sigmap, const SigPool &driven_signals) {
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if (sig.is_fully_const())
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return SigDirection::DRIVEN;
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bool has_input = false;
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bool has_output = false;
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bool has_driven = false;
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bool has_unknown = false;
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for (auto &chunk : sig.chunks()) {
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if (chunk.is_wire()) {
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Wire *w = chunk.wire;
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if (w->port_input && w->port_output) {
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has_input = true;
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has_output = true;
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} else if (w->port_input) {
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has_input = true;
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} else if (w->port_output) {
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has_output = true;
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} else {
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SigSpec chunk_sig = sigmap(SigSpec(chunk));
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if (driven_signals.check_any(chunk_sig)) {
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has_driven = true;
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} else {
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has_unknown = true;
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}
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}
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}
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}
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if (has_input && has_output)
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return SigDirection::INOUT;
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if (has_output || has_driven)
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return SigDirection::OUTPUT;
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if (has_input)
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return SigDirection::INPUT;
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if (has_unknown)
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return SigDirection::UNKNOWN;
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return SigDirection::DRIVEN;
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}
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void check_and_adjust_ports(Module* module, std::set<Module*>& blackbox_derivatives, bool keep_portwidths, bool top_is_from_verific) {
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Design* design = module->design;
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for (auto cell : module->cells())
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{
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Module *m = design->module(cell->type);
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if (m == nullptr)
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continue;
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bool boxed_params = false;
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if (m->get_blackbox_attribute() && !cell->parameters.empty()) {
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if (m->get_bool_attribute(ID::dynports)) {
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IdString new_m_name = m->derive(design, cell->parameters, true);
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if (new_m_name.empty())
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continue;
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if (new_m_name != m->name) {
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m = design->module(new_m_name);
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blackbox_derivatives.insert(m);
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}
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} else {
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boxed_params = true;
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}
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}
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for (auto &conn : cell->connections())
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{
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Wire *w = m->wire(conn.first);
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if (w == nullptr || w->port_id == 0)
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continue;
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if (GetSize(conn.second) == 0)
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continue;
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SigSpec sig = conn.second;
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bool resize_widths = !keep_portwidths && GetSize(w) != GetSize(conn.second);
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if (resize_widths && top_is_from_verific && boxed_params)
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log_debug("Ignoring width mismatch on %s.%s.%s from verific, is port width parametrizable?\n",
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log_id(module), log_id(cell), log_id(conn.first)
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);
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else if (resize_widths) {
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if (GetSize(w) < GetSize(conn.second))
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{
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int n = GetSize(conn.second) - GetSize(w);
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if (!w->port_input && w->port_output)
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{
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RTLIL::SigSpec out = sig.extract(0, GetSize(w));
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out.extend_u0(GetSize(sig), w->is_signed);
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module->connect(sig.extract(GetSize(w), n), out.extract(GetSize(w), n));
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}
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sig.remove(GetSize(w), n);
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}
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else
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{
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int n = GetSize(w) - GetSize(conn.second);
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if (w->port_input && !w->port_output)
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sig.extend_u0(GetSize(w), sig.is_wire() && sig.as_wire()->is_signed);
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else
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sig.append(module->addWire(NEW_ID, n));
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}
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if (!conn.second.is_fully_const() || !w->port_input || w->port_output)
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log_warning("Resizing cell port %s.%s.%s from %d bits to %d bits.\n", log_id(module), log_id(cell),
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log_id(conn.first), GetSize(conn.second), GetSize(sig));
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cell->setPort(conn.first, sig);
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}
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if (w->port_output && !w->port_input && sig.has_const())
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log_error("Output port %s.%s.%s (%s) is connected to constants: %s\n",
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log_id(module), log_id(cell), log_id(conn.first), log_id(cell->type), log_signal(sig));
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}
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}
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}
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bool resolve_connect_directionality(Module* module) {
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bool did_something = false;
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int iteration = 0;
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while (true) {
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iteration++;
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pool<Cell*> cells_to_remove;
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vector<SigSig> new_connections;
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SigMap sigmap(module);
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SigPool driven_signals;
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build_driven_signals_index(module, sigmap, driven_signals);
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for (auto cell : module->cells())
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{
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if (cell->type != ID($connect))
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continue;
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if (cell->has_keep_attr())
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continue;
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SigSpec sig_a = cell->getPort(ID::A);
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SigSpec sig_b = cell->getPort(ID::B);
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if (sig_a.size() == 0 || sig_b.size() == 0)
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continue;
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SigDirection dir_a = get_signal_direction(sig_a, sigmap, driven_signals);
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SigDirection dir_b = get_signal_direction(sig_b, sigmap, driven_signals);
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SigSpec driver, driven;
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bool can_resolve = false;
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if ((dir_a == SigDirection::OUTPUT || dir_a == SigDirection::DRIVEN) && dir_b == SigDirection::INPUT) {
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driver = sig_a;
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driven = sig_b;
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can_resolve = true;
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}
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else if (dir_a == SigDirection::INPUT && (dir_b == SigDirection::OUTPUT || dir_b == SigDirection::DRIVEN)) {
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driver = sig_b;
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driven = sig_a;
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can_resolve = true;
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}
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else if (dir_a == SigDirection::DRIVEN && dir_b == SigDirection::UNKNOWN) {
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driver = sig_a;
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driven = sig_b;
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can_resolve = true;
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}
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else if (dir_a == SigDirection::UNKNOWN && dir_b == SigDirection::DRIVEN) {
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driver = sig_b;
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driven = sig_a;
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can_resolve = true;
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}
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else {
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continue;
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}
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if (can_resolve) {
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log_debug("Resolving $connect %s: %s <- %s\n", log_id(cell), log_signal(driven), log_signal(driver));
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new_connections.push_back({driven, driver});
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cells_to_remove.insert(cell);
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}
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}
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for (auto &conn : new_connections)
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module->connect(conn);
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for (auto cell : cells_to_remove)
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module->remove(cell);
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if (cells_to_remove.empty())
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break;
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did_something = true;
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log_debug("$connect res iteration %d: resolved %d cells\n", iteration, GetSize(cells_to_remove));
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}
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return did_something;
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}
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};
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YOSYS_NAMESPACE_END
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