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36 lines
651 B
Verilog
36 lines
651 B
Verilog
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// from usb_rx_phy
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module usb_phy_test01(clk, rst, rx_en, fs_ce);
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input clk, rst;
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input rx_en;
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output reg fs_ce;
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reg [1:0] dpll_next_state;
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reg [1:0] dpll_state;
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always @(posedge clk)
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dpll_state <= rst ? 0 : dpll_next_state;
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always @*
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begin
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fs_ce = 1'b0;
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case(dpll_state)
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2'h0:
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if(rx_en) dpll_next_state = 2'h0;
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else dpll_next_state = 2'h1;
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2'h1:begin
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fs_ce = 1'b1;
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if(rx_en) dpll_next_state = 2'h3;
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else dpll_next_state = 2'h2;
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end
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2'h2:
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if(rx_en) dpll_next_state = 2'h0;
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else dpll_next_state = 2'h3;
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2'h3:
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if(rx_en) dpll_next_state = 2'h0;
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else dpll_next_state = 2'h0;
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endcase
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end
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endmodule
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