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https://github.com/YosysHQ/yosys
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84 lines
1.3 KiB
Verilog
84 lines
1.3 KiB
Verilog
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module blocking_cond (in, out);
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input in;
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output reg out;
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reg tmp;
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always @* begin
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tmp = 1;
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out = 1'b0;
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case (1'b1)
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tmp: out = in;
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endcase
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tmp = 0;
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end
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endmodule
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// -------------------------------------------------------------
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module uut(clk, arst, a, b, c, d, e, f, out1);
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input clk, arst, a, b, c, d, e, f;
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output reg [3:0] out1;
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always @(posedge clk, posedge arst) begin
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if (arst)
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out1 = 0;
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else begin
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if (a) begin
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case ({b, c})
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2'b00:
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out1 = out1 + 9;
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2'b01, 2'b10:
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out1 = out1 + 13;
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endcase
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if (d) begin
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out1 = out1 + 2;
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out1 = out1 + 1;
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end
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case ({e, f})
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2'b11:
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out1 = out1 + 8;
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2'b00:
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;
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default:
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out1 = out1 + 10;
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endcase
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out1 = out1 ^ 7;
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end
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out1 = out1 + 14;
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end
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end
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endmodule
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// -------------------------------------------------------------
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// extracted from ../asicworld/code_hdl_models_uart.v
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// (triggered a bug in the proc_mux pass)
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module uart (reset, txclk, ld_tx_data, tx_empty, tx_cnt);
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input reset;
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input txclk;
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input ld_tx_data;
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output reg tx_empty;
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output reg [3:0] tx_cnt;
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always @ (posedge txclk)
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if (reset) begin
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tx_empty <= 1;
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tx_cnt <= 0;
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end else begin
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if (ld_tx_data) begin
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tx_empty <= 0;
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end
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if (!tx_empty) begin
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tx_cnt <= tx_cnt + 1;
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end
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end
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endmodule
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