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	If all the (non-select) inputs of a `$_MUX{4,8,16}_` are undefined, replace it, just like we do for `$mux` and `$_MUX_`.
Add `tests/opt/opt_expr_mux_undef.ys` to verify this.
This doesn't do any const folding on the wide muxes, or shrinking to less wide muxes.  It only handles the case where all inputs are 'x and the mux can be completely removed.
		
	
			
		
			
				
	
	
		
			290 lines
		
	
	
	
		
			4.4 KiB
		
	
	
	
		
			Text
		
	
	
	
	
	
			
		
		
	
	
			290 lines
		
	
	
	
		
			4.4 KiB
		
	
	
	
		
			Text
		
	
	
	
	
	
| 
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| read_rtlil <<EOT
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| module \uut
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|   wire output 1 \out
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|   wire input 2 width 16 \in
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|   wire input 3 width 4 \sel
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|   cell $_MUX16_ \mux
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|     connect \A \in [0]
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|     connect \B \in [1]
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|     connect \C \in [2]
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|     connect \D \in [3]
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|     connect \E \in [4]
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|     connect \F \in [5]
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|     connect \G \in [6]
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|     connect \H \in [7]
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|     connect \I \in [8]
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|     connect \J \in [9]
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|     connect \K \in [10]
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|     connect \L \in [11]
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|     connect \M \in [12]
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|     connect \N \in [13]
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|     connect \O \in [14]
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|     connect \P \in [15]
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|     connect \S \sel [0]
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|     connect \T \sel [1]
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|     connect \U \sel [2]
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|     connect \V \sel [3]
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|     connect \Y \out
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|   end
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| end
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| EOT
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| 
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| ##########
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| # all undef
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| # no mux
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| # output undef
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| 
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| design -reset
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| read_rtlil <<EOT
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| module \uut
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|   wire output 1 \out
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|   cell $mux \mux
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|     parameter \WIDTH 1
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|     connect \A 1'x
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|     connect \B 1'x
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|     connect \S 1'x
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|     connect \Y \out
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|   end
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| end
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| EOT
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| 
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| opt_expr -mux_undef
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| select -assert-none t:$mux
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| select -assert-count 1 o:out %ci*
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| 
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| ##
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| 
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| design -reset
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| read_rtlil <<EOT
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| module \uut
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|   wire output 1 \out
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|   cell $_MUX_ \mux
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|     connect \A 1'x
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|     connect \B 1'x
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|     connect \S 1'x
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|     connect \Y \out
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|   end
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| end
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| EOT
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| 
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| opt_expr -mux_undef
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| select -assert-none t:$_MUX_
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| select -assert-count 1 o:out %ci*
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| 
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| ##
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| 
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| design -reset
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| read_rtlil <<EOT
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| module \uut
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|   wire output 1 \out
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|   cell $_MUX4_ \mux
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|     connect \A 1'x
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|     connect \B 1'x
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|     connect \C 1'x
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|     connect \D 1'x
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|     connect \S 1'x
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|     connect \T 1'x
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|     connect \Y \out
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|   end
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| end
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| EOT
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| 
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| opt_expr -mux_undef
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| select -assert-none t:$_MUX4_
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| 
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| ##
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| 
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| design -reset
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| read_rtlil <<EOT
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| module \uut
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|   wire output 1 \out
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|   cell $_MUX8_ \mux
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|     connect \A 1'x
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|     connect \B 1'x
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|     connect \C 1'x
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|     connect \D 1'x
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|     connect \E 1'x
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|     connect \F 1'x
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|     connect \G 1'x
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|     connect \H 1'x
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|     connect \S 1'x
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|     connect \T 1'x
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|     connect \U 1'x
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|     connect \Y \out
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|   end
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| end
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| EOT
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| 
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| opt_expr -mux_undef
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| select -assert-none t:$_MUX8_
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| 
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| ##
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| 
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| design -reset
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| read_rtlil <<EOT
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| module \uut
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|   wire output 1 \out
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|   cell $_MUX16_ \mux
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|     connect \A 1'x
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|     connect \B 1'x
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|     connect \C 1'x
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|     connect \D 1'x
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|     connect \E 1'x
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|     connect \F 1'x
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|     connect \G 1'x
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|     connect \H 1'x
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|     connect \I 1'x
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|     connect \J 1'x
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|     connect \K 1'x
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|     connect \L 1'x
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|     connect \M 1'x
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|     connect \N 1'x
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|     connect \O 1'x
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|     connect \P 1'x
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|     connect \S 1'x
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|     connect \T 1'x
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|     connect \U 1'x
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|     connect \V 1'x
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|     connect \Y \out
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|   end
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| end
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| EOT
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| 
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| opt_expr -mux_undef
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| select -assert-none t:$_MUX16_
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| 
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| ##########
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| # a and b undef
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| # no mux
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| # output undef
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| 
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| design -reset
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| read_rtlil <<EOT
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| module \uut
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|   wire output 1 \out
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|   wire input 3 \sel
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|   cell $mux \mux
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|     parameter \WIDTH 1
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|     connect \A 1'x
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|     connect \B 1'x
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|     connect \S \sel
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|     connect \Y \out
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|   end
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| end
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| EOT
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| 
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| opt_expr -mux_undef
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| select -assert-none t:$mux
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| select -assert-count 1 o:out %ci*
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| 
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| ##
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| 
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| design -reset
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| read_rtlil <<EOT
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| module \uut
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|   wire output 1 \out
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|   wire input 3 \sel
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|   cell $_MUX_ \mux
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|     connect \A 1'x
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|     connect \B 1'x
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|     connect \S \sel
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|     connect \Y \out
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|   end
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| end
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| EOT
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| 
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| opt_expr -mux_undef
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| select -assert-none t:$_MUX_
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| select -assert-count 1 o:out %ci*
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| 
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| ##
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| 
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| design -reset
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| read_rtlil <<EOT
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| module \uut
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|   wire output 1 \out
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|   wire input 3 width 2 \sel
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|   cell $_MUX4_ \mux
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|     connect \A 1'x
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|     connect \B 1'x
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|     connect \C 1'x
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|     connect \D 1'x
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|     connect \S \sel [0]
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|     connect \T \sel [1]
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|     connect \Y \out
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|   end
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| end
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| EOT
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| 
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| opt_expr -mux_undef
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| select -assert-none t:$_MUX4_
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| select -assert-count 1 o:out %ci*
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| 
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| ##
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| 
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| design -reset
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| read_rtlil <<EOT
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| module \uut
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|   wire output 1 \out
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|   wire input 3 width 3 \sel
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|   cell $_MUX8_ \mux
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|     connect \A 1'x
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|     connect \B 1'x
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|     connect \C 1'x
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|     connect \D 1'x
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|     connect \E 1'x
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|     connect \F 1'x
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|     connect \G 1'x
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|     connect \H 1'x
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|     connect \S \sel [0]
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|     connect \T \sel [1]
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|     connect \U \sel [2]
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|     connect \Y \out
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|   end
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| end
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| EOT
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| 
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| opt_expr -mux_undef
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| select -assert-none t:$_MUX8_
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| select -assert-count 1 o:out %ci*
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| 
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| ##
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| 
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| design -reset
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| read_rtlil <<EOT
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| module \uut
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|   wire output 1 \out
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|   wire input 3 width 4 \sel
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|   cell $_MUX16_ \mux
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|     connect \A 1'x
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|     connect \B 1'x
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|     connect \C 1'x
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|     connect \D 1'x
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|     connect \E 1'x
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|     connect \F 1'x
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|     connect \G 1'x
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|     connect \H 1'x
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|     connect \I 1'x
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|     connect \J 1'x
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|     connect \K 1'x
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|     connect \L 1'x
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|     connect \M 1'x
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|     connect \N 1'x
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|     connect \O 1'x
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|     connect \P 1'x
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|     connect \S \sel [0]
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|     connect \T \sel [1]
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|     connect \U \sel [2]
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|     connect \V \sel [3]
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|     connect \Y \out
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|   end
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| end
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| EOT
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| 
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| opt_expr -mux_undef
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| select -assert-none t:$_MUX16_
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| select -assert-count 1 o:out %ci*
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| 
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| ##########
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| 
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