mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 03:32:29 +00:00
d41688f7d7
* area should be 1 for all LUTs * clean up macros * add log_assert to fail noisily when encountering oddly configured DFF * clean help msg * flatten set to true by default * update * merge mult tests * remove redundant test * move all dsp tests to single file and remove redundant tests * update ram tests * add more dff tests * fix c++20 compile errors * add option to dump verilog * default to use abc9 * remove -abc9 option since its the default now --------- Co-authored-by: tony <minchunlin@gmail.com>
76 lines
No EOL
2.3 KiB
Text
76 lines
No EOL
2.3 KiB
Text
# ISC License
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#
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# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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#
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# Permission to use, copy, modify, and/or distribute this software for any
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# purpose with or without fee is hereby granted, provided that the above
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# copyright notice and this permission notice appear in all copies.
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#
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# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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# active low async reset with enable
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read_verilog <<EOT
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module top(
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input clk,
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input en,
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input rst,
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input D,
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output reg Q
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);
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always @(posedge clk, negedge rst) begin
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if (rst == 0) begin
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Q <= 1;
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end else if(en) begin
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Q <= D;
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end
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end
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endmodule
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EOT
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synth_microchip -top top -family polarfire -noiopad
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select -assert-count 1 t:SLE
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select -assert-count 1 t:CLKBUF
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select -assert-none t:SLE t:CLKBUF %% t:* %D
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design -reset
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read_verilog -D NO_INIT ../common/dffs.v
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synth_microchip -top dff -family polarfire -noiopad
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select -assert-count 1 t:SLE
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select -assert-count 1 t:CLKBUF
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select -assert-none t:SLE t:CLKBUF %% t:* %D
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design -reset
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read_verilog -D NO_INIT ../common/dffs.v
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synth_microchip -top dffe -family polarfire -noiopad
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select -assert-count 1 t:SLE
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select -assert-count 1 t:CLKBUF
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select -assert-none t:SLE t:CLKBUF %% t:* %D
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design -reset
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read_verilog -D NO_INIT ../common/adffs.v
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synth_microchip -top adff -family polarfire -noiopad
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select -assert-count 1 t:SLE
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select -assert-count 1 t:CLKBUF
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select -assert-count 1 t:CFG1
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select -assert-none t:SLE t:CLKBUF t:CFG1 %% t:* %D
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design -reset
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read_verilog -D NO_INIT ../common/adffs.v
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synth_microchip -top adffn -family polarfire -noiopad
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select -assert-count 1 t:SLE
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select -assert-count 1 t:CLKBUF
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select -assert-none t:SLE t:CLKBUF %% t:* %D
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design -reset
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read_verilog -D NO_INIT ../common/adffs.v
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synth_microchip -top dffs -family polarfire -noiopad
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select -assert-count 1 t:SLE
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select -assert-count 1 t:CLKBUF
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select -assert-count 1 t:CFG1
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select -assert-none t:SLE t:CLKBUF t:CFG1 %% t:* %D |