mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 03:32:29 +00:00
21 lines
360 B
Verilog
21 lines
360 B
Verilog
module latchp ( input d, clk, en, output reg q );
|
|
always @*
|
|
if ( en )
|
|
q <= d;
|
|
endmodule
|
|
|
|
module latchn ( input d, clk, en, output reg q );
|
|
always @*
|
|
if ( !en )
|
|
q <= d;
|
|
endmodule
|
|
|
|
module latchsr ( input d, clk, en, clr, pre, output reg q );
|
|
always @*
|
|
if ( clr )
|
|
q <= 1'b0;
|
|
else if ( pre )
|
|
q <= 1'b1;
|
|
else if ( en )
|
|
q <= d;
|
|
endmodule
|