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https://github.com/YosysHQ/yosys
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105 lines
2.8 KiB
Verilog
105 lines
2.8 KiB
Verilog
/*
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ISC License
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Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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Permission to use, copy, modify, and/or distribute this software for any
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purpose with or without fee is hereby granted, provided that the above
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copyright notice and this permission notice appear in all copies.
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THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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// Based on Macro Library for PolarFire https://coredocs.s3.amazonaws.com/Libero/2021_2/Tool/pf_mlg.pdf
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// NOTE: prefix module names with \$__ so that mapping prioritizes these cells over internal Yosys cells
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(* techmap_celltype = "$_MUX4_" *)
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module \$__microchip_MUX4_ (A, B, C, D, S, T, Y);
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input A, B, C, D, S, T;
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output Y;
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MX4 _TECHMAP_REPLACE_.MUX4(.D3(D), .D2(C), .D1(B), .D0(A), .S1(T), .S0(S), .Y(Y));
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endmodule
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(* techmap_celltype = "$reduce_xor" *)
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module \$__microchip_XOR8_ (A, Y);
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parameter A_SIGNED = 1;
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parameter A_WIDTH = 8;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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output [Y_WIDTH-1:0] Y;
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// check if mapping should proceed
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generate
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if (A_WIDTH != 8 || A_SIGNED || Y_WIDTH != 1) begin
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wire _TECHMAP_FAIL_ = 1;
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end
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endgenerate
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XOR8 _TECHMAP_REPLACE_.XOR8 (.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .E(A[4]), .F(A[5]), .G(A[6]), .H(A[7]), .Y(Y));
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endmodule
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(* techmap_celltype = "$alu" *)
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module \$__SF2_ALU (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] X, Y;
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input CI, BI;
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(* force_downto *)
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output [Y_WIDTH-1:0] CO;
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wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
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(* force_downto *)
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wire [Y_WIDTH-1:0] AA, BB;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(AA));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(BB));
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(* force_downto *)
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wire [Y_WIDTH-1:0] C = {CO, CI};
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genvar i;
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generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
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ARI1 #(
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// See section 1.4 of PolarFire Macro Library
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// G = F1 = A[i] & (B[i]^BI)
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// Y = F0 = A[i]^B[i]^BI
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// P = Y
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// ADCB
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.INIT(20'b 01_11_0010_1000_1001_0110)
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) carry (
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.A(1'b0),
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.B(AA[i]),
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.C(BB[i]),
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.D(BI),
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.FCI(C[i]),
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.Y(X[i]),
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.S(Y[i]),
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.FCO(CO[i])
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);
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end endgenerate
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endmodule
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