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73 lines
2 KiB
Verilog
73 lines
2 KiB
Verilog
module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 0;
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parameter B_WIDTH = 0;
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parameter Y_WIDTH = 0;
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wire [A_WIDTH+B_WIDTH-1:0] mult_result;
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fiftyfivenm_mac_mult #(
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.dataa_clock ("none"),
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.datab_clock ("none"),
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.signa_clock ("none"),
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.signb_clock ("none"),
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.dataa_width (A_WIDTH),
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.datab_width (B_WIDTH),
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.lpm_type ("fiftyfivenm_mac_mult")
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) _TECHMAP_REPLACE_mac_mult (
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//Data path
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.dataa ( A ),
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.datab ( B ),
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.dataout( mult_result ),
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.signa ( A_SIGNED != 0 ? 1'b1 : 1'b0),
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.signb ( B_SIGNED != 0 ? 1'b1 : 1'b0)
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);
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fiftyfivenm_mac_out #(
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.dataa_width (A_WIDTH + B_WIDTH),
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.output_clock ("none"),
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.lpm_type ("fiftyfivenm_mac_out")
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) _TECHMAP_REPLACE_mac_out (
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.dataa (mult_result),
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.dataout (Y)
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);
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endmodule
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module \$__MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 0;
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parameter B_WIDTH = 0;
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parameter Y_WIDTH = 0;
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wire [A_WIDTH+B_WIDTH-1:0] mult_result;
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fiftyfivenm_mac_mult #(
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.dataa_clock ("none"),
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.datab_clock ("none"),
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.signa_clock ("none"),
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.signb_clock ("none"),
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.dataa_width (A_WIDTH),
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.datab_width (B_WIDTH),
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.lpm_type ("fiftyfivenm_mac_mult")
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) _TECHMAP_REPLACE_mac_mult (
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//Data path
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.dataa ( A ),
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.datab ( B ),
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.dataout( mult_result ),
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.signa ( A_SIGNED != 0 ? 1'b1 : 1'b0),
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.signb ( B_SIGNED != 0 ? 1'b1 : 1'b0)
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);
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fiftyfivenm_mac_out #(
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.dataa_width (A_WIDTH + B_WIDTH),
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.output_clock ("none"),
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.lpm_type ("fiftyfivenm_mac_out")
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) _TECHMAP_REPLACE_mac_out (
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.dataa (mult_result),
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.dataout (Y)
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);
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endmodule
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