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12 lines
231 B
Verilog
12 lines
231 B
Verilog
// Simple exists-forall demo
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module demo8;
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wire [7:0] prime = $anyconst;
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wire [3:0] factor = $allconst;
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always @* begin
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if (1 < factor && factor < prime)
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assume((prime % factor) != 0);
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assume(prime > 1);
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end
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endmodule
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