mirror of
https://github.com/YosysHQ/yosys
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72787f52fc
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
105 lines
3.2 KiB
Verilog
105 lines
3.2 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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/* TODO: Describe the following mode */
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module fa
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(input a_c,
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input b_c,
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input cin_c,
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output cout_t,
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output sum_x);
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wire a_c;
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wire b_c;
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wire cout_t;
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wire cin_c;
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wire sum_x;
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wire VCC;
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assign VCC = 1'b1;
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cycloneiv_lcell_comb gen_sum_0 (.combout(sum_x),
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.dataa(a_c),
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.datab(b_c),
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.datac(cin_c),
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.datad(VCC));
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defparam syn__05_.lut_mask = 16'b1001011010010110;
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defparam syn__05_.sum_lutc_input = "datac";
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cycloneiv_lcell_comb gen_cout_0 (.combout(cout_t),
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.dataa(cin_c),
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.datab(b_c),
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.datac(a_c),
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.datad(VCC));
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defparam syn__06_.lut_mask = 16'b1110000011100000;
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defparam syn__06_.sum_lutc_input = "datac";
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endmodule // fa
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module f_stage();
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endmodule // f_stage
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module f_end();
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endmodule // f_end
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module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] X, Y;
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input CI, BI;
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output [Y_WIDTH:0] CO;
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wire _TECHMAP_FAIL_ = Y_WIDTH < 5;
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(* force_downto *)
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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(* force_downto *)
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wire [Y_WIDTH-1:0] AA = A_buf;
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(* force_downto *)
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wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
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wire [Y_WIDTH:0] C = {CO, CI};
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fa f0 (.a_c(AA[0]),
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.b_c(BB[0]),
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.cin_c(C[0]),
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.cout_t(C0[1]),
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.sum_x(Y[0]));
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genvar i;
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generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice
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cycloneive_lcell_comb #(.lut_mask(16'b0101_1010_0101_0000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(CO[i]), .dataa(BB[i]), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[i]));
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end endgenerate
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assign X = AA ^ BB;
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endmodule
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