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https://github.com/YosysHQ/yosys
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2a3720921c
For these primitives, Gowin decided to use a different option for describing ports—directly in the module header, i.e. ``` verilog module ADC(input CLK); ``` instead of ``` verilog module ADC(CLK); input CLK; ``` Since this one-time parser becomes too confusing, it is easier to simply add ADC descriptions as they are from a separate file, especially since these primitives are only available in the GW5A series. Test: ``` shell yosys -p "read_verilog top.v; synth_gowin -json top-synth.json -family gw5a" ``` The old version of Yosys simply won't compile the design due to the lack of port descriptions, while the new version will compile without errors. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
106 lines
4.4 KiB
Python
106 lines
4.4 KiB
Python
#!/usr/bin/env python3
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# Base on Nexus cells_xtra.py
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from argparse import ArgumentParser
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import os.path
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from enum import Enum, auto
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import sys
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import re
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class State(Enum):
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OUTSIDE = auto()
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IN_MODULE = auto()
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IN_MODULE_MULTILINE = auto()
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IN_PARAMETER = auto()
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_skip = { # These are already described, no need to extract them from the vendor files
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'ALU', 'BANDGAP', 'DFF', 'DFFC', 'DFFCE', 'DFFE', 'DFFN', 'DFFNC', 'DFFNCE',
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'DFFNE', 'DFFNP', 'DFFNPE', 'DFFNR', 'DFFNRE', 'DFFNS', 'DFFNSE',
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'DFFP', 'DFFPE', 'DFFR', 'DFFRE', 'DFFS', 'DFFSE', 'DP', 'DPX9',
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'ELVDS_OBUF', 'GND', 'GSR', 'IBUF', 'IDDR', 'IDDRC', 'IDES10',
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'IDES16', 'IDES4', 'IDES8', 'IOBUF', 'IVIDEO', 'LUT1', 'LUT2',
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'LUT3', 'LUT4', 'MUX2', 'MUX2_LUT5', 'MUX2_LUT6', 'MUX2_LUT7',
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'MUX2_LUT8', 'OBUF', 'ODDR', 'ODDRC', 'OSC', 'OSCF', 'OSCH',
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'OSCO', 'OSCW', 'OSCZ', 'OSER10', 'OSER16', 'OSER10', 'OSER4',
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'OSER8', 'OVIDEO', 'PLLVR', 'RAM16S1', 'RAM16S2', 'RAM16S4',
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'RAM16SDP1', 'RAM16SDP2', 'RAM16SDP4', 'rPLL', 'SDP',
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'SDPX9', 'SP', 'SPX9', 'TBUF', 'TLVDS_OBUF', 'VCC', 'EMCU',
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# These are not planned for implementation
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'MUX2_MUX8', 'MUX2_MUX16', 'MUX2_MUX32', 'MUX4', 'MUX8', 'MUX16',
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'MUX32', 'DL', 'DLE', 'DLC', 'DLCE', 'DLP', 'DLPE', 'DLN', 'DLNE',
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'DLNC', 'DLNCE', 'DLNP', 'DLNPE', 'rSDP', 'rSDPX9', 'rROM', 'rROMX9',
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'TLVDS_OEN_BK', 'DLL', 'DCC', 'I3C', 'IODELAYA', 'IODELAYC', 'IODELAYB',
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'SPMI', 'PLLO', 'DCCG', 'MIPI_DPHY_RX', 'CLKDIVG', 'PWRGRD', 'FLASH96KA',
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# ADCs are in a separate file
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'ADCLRC', 'ADCULC', 'ADC', 'ADC_SAR', 'ADCA',
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}
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def xtract_cells_decl(dir, fout):
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fname = os.path.join(dir, 'prim_sim.v')
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with open(fname) as f:
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state = State.OUTSIDE
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for l in f:
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l, _, comment = l.partition('//')
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if l.startswith("module "):
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cell_name = l[7:l.find('(')].strip()
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if cell_name not in _skip:
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state = State.IN_MODULE
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fout.write(f'\nmodule {cell_name} (...);\n')
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elif l.startswith(('input', 'output', 'inout')) and state == State.IN_MODULE:
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fout.write(l)
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if l[-1] != '\n':
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fout.write('\n')
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if l.rstrip()[-1] != ';':
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state = State.IN_MODULE_MULTILINE
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elif l.lstrip().startswith('parameter') and state == State.IN_MODULE:
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fout.write(l)
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if l.rstrip()[-1] == ',':
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state = State.IN_PARAMETER
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if l[-1] != '\n':
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fout.write('\n')
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elif l and state == State.IN_MODULE_MULTILINE:
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fout.write(l)
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if l[-1] != '\n':
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fout.write('\n')
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if l.rstrip()[-1] == ';':
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state = State.IN_MODULE
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elif state == State.IN_PARAMETER:
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fout.write(l)
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if l.rstrip()[-1] == ';':
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state = State.IN_MODULE
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if l[-1] != '\n':
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fout.write('\n')
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elif l.startswith('endmodule') and state == State.IN_MODULE:
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state = State.OUTSIDE
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fout.write('endmodule\n')
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if l[-1] != '\n':
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fout.write('\n')
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if __name__ == '__main__':
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parser = ArgumentParser(description='Extract Gowin blackbox cell definitions.')
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parser.add_argument('gowin_dir', nargs='?', default='/opt/gowin/')
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args = parser.parse_args()
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families = {
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'gw1n': os.path.join(args.gowin_dir, 'IDE/simlib/gw1n/'),
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'gw2a': os.path.join(args.gowin_dir, 'IDE/simlib/gw2a/'),
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'gw5a': os.path.join(args.gowin_dir, 'IDE/simlib/gw5a/'),
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}
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for family, dir in families.items():
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if not os.path.isdir(dir):
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print(f'{dir} is not a directory')
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else:
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with open(f'cells_xtra_{family}.v', 'w') as fout:
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fout.write('// Created by cells_xtra.py\n')
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fout.write('\n')
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xtract_cells_decl(dir, fout)
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if family == 'gw5a':
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fout.write('\n')
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fout.write('// Added from adc.v\n')
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fout.write('\n')
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with open(f'adc.v', 'r') as fin:
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for l in fin:
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fout.write(l);
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