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19 lines
220 B
Systemverilog
19 lines
220 B
Systemverilog
module top (
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input clk,
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input a, b
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);
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default clocking @(posedge clk); endclocking
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assert property (
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$changed(b)
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);
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wire x = 'x;
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`ifndef FAIL
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assume property (
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b !== x ##1 $changed(b)
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);
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`endif
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endmodule
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