mirror of
https://github.com/YosysHQ/yosys
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| .. | ||
| .gitignore | ||
| cy_cells.v | ||
| generate.cc | ||
| Makefile | ||
| README | ||
| report.sh | ||
| run-check.sh | ||
| run-quartus.sh | ||
| run-vivado.sh | ||
| run-xst.sh | ||
| xl_cells.v | ||
| xl_cells_tb.v | ||
| xl_cells_tb.ys | ||
================================ This is work under construction! ================================ This is going to be a collection of auto-generated test cases. The goal is to synthesize them with Yosys and Xilinx XST and perform formal equivialence checks using the Yosys SAT-based equivialence checker. This will hopefully reveal some bugs in both applications.. ;-) Simply run 'make' to generate all test cases and run all the tests. (Use 'make -j N' to use N parallel cores.)