Eddie Hung e658d472c8 Put attributes above port		2019-08-23 11:31:20 -07:00
..
tests
.gitignore
abc_map.v	xilinx to use abc_map.v with -max_iter 1	2019-08-20 19:47:11 -07:00
abc_model.v	xilinx to use abc_map.v with -max_iter 1	2019-08-20 19:47:11 -07:00
abc_unmap.v	xilinx to use abc_map.v with -max_iter 1	2019-08-20 19:47:11 -07:00
abc_xc7.box	xilinx to use abc_map.v with -max_iter 1	2019-08-20 19:47:11 -07:00
abc_xc7.lut
abc_xc7_nowide.lut
arith_map.v
brams_init.py
cells_map.v	Use abc_{map,unmap,model}.v	2019-08-20 12:39:11 -07:00
cells_sim.v	Put attributes above port	2019-08-23 11:31:20 -07:00
cells_xtra.sh
cells_xtra.v
ff_map.v
lut_map.v
lutrams.txt
lutrams_map.v
Makefile.inc	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-08-20 17:36:14 -07:00
mux_map.v
synth_xilinx.cc	Use semicolon	2019-08-21 11:47:17 -07:00
xc6s_brams.txt
xc6s_brams_bb.v
xc6s_brams_map.v
xc7_brams.txt
xc7_brams_bb.v	Put attributes above port	2019-08-23 11:31:20 -07:00
xc7_brams_map.v