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794 lines
15 KiB
Verilog
794 lines
15 KiB
Verilog
`timescale 1ns/1ps
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/*
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This file contains simulation models for GreenPAK cells which are possible to fully model using synthesizeable
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behavioral Verilog constructs only.
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*/
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module GP_2LUT(input IN0, IN1, output OUT);
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parameter [3:0] INIT = 0;
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assign OUT = INIT[{IN1, IN0}];
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endmodule
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module GP_3LUT(input IN0, IN1, IN2, output OUT);
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parameter [7:0] INIT = 0;
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assign OUT = INIT[{IN2, IN1, IN0}];
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endmodule
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module GP_4LUT(
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input wire IN0,
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input wire IN1,
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input wire IN2,
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input wire IN3,
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output wire OUT);
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parameter [15:0] INIT = 0;
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assign OUT = INIT[{IN3, IN2, IN1, IN0}];
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endmodule
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module GP_CLKBUF(input wire IN, output wire OUT);
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assign OUT = IN;
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endmodule
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module GP_COUNT14(input CLK, input wire RST, output reg OUT);
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parameter RESET_MODE = "RISING";
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parameter COUNT_TO = 14'h1;
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parameter CLKIN_DIVIDE = 1;
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reg[13:0] count = COUNT_TO;
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initial begin
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if(CLKIN_DIVIDE != 1) begin
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$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
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$finish;
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end
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end
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//Combinatorially output underflow flag whenever we wrap low
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always @(*) begin
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OUT = (count == 14'h0);
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end
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//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
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//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
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generate
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case(RESET_MODE)
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"RISING": begin
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always @(posedge CLK, posedge RST) begin
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if(RST)
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count <= 0;
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else begin
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count <= count - 1'd1;
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if(count == 0)
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count <= COUNT_TO;
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end
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end
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end
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"FALLING": begin
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always @(posedge CLK, negedge RST) begin
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if(!RST)
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count <= 0;
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else begin
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count <= count - 1'd1;
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if(count == 0)
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count <= COUNT_TO;
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end
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end
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end
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"BOTH": begin
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initial begin
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$display("Both-edge reset mode for GP_COUNT14 not implemented");
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$finish;
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end
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end
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"LEVEL": begin
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always @(posedge CLK, posedge RST) begin
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if(RST)
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count <= 0;
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else begin
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count <= count - 1'd1;
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if(count == 0)
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count <= COUNT_TO;
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end
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end
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end
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default: begin
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initial begin
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$display("Invalid RESET_MODE on GP_COUNT14");
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$finish;
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end
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end
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endcase
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endgenerate
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endmodule
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module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
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input UP, input KEEP, output reg[7:0] POUT);
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parameter RESET_MODE = "RISING";
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parameter RESET_VALUE = "ZERO";
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parameter COUNT_TO = 14'h1;
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parameter CLKIN_DIVIDE = 1;
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initial begin
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if(CLKIN_DIVIDE != 1) begin
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$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
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$finish;
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end
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end
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reg[13:0] count = COUNT_TO;
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//Combinatorially output underflow flag whenever we wrap low
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always @(*) begin
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if(UP)
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OUT = (count == 14'h3fff);
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else
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OUT = (count == 14'h0);
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POUT = count[7:0];
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end
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//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
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//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
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generate
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case(RESET_MODE)
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"RISING": begin
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always @(posedge CLK, posedge RST) begin
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//Resets
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if(RST) begin
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if(RESET_VALUE == "ZERO")
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count <= 0;
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else
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count <= COUNT_TO;
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end
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else if(KEEP) begin
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end
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else if(UP) begin
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count <= count + 1'd1;
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if(count == 14'h3fff)
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count <= COUNT_TO;
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end
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else begin
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count <= count - 1'd1;
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if(count == 0)
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count <= COUNT_TO;
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end
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end
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end
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"FALLING": begin
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always @(posedge CLK, negedge RST) begin
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//Resets
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if(!RST) begin
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if(RESET_VALUE == "ZERO")
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count <= 0;
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else
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count <= COUNT_TO;
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end
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else if(KEEP) begin
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end
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else if(UP) begin
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count <= count + 1'd1;
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if(count == 14'h3fff)
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count <= COUNT_TO;
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end
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else begin
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count <= count - 1'd1;
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if(count == 0)
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count <= COUNT_TO;
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end
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end
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end
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"BOTH": begin
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initial begin
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$display("Both-edge reset mode for GP_COUNT14_ADV not implemented");
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$finish;
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end
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end
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"LEVEL": begin
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always @(posedge CLK, posedge RST) begin
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//Resets
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if(RST) begin
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if(RESET_VALUE == "ZERO")
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count <= 0;
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else
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count <= COUNT_TO;
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end
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else begin
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if(KEEP) begin
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end
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else if(UP) begin
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count <= count + 1'd1;
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if(count == 14'h3fff)
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count <= COUNT_TO;
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end
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else begin
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count <= count - 1'd1;
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if(count == 0)
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count <= COUNT_TO;
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end
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end
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end
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end
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default: begin
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initial begin
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$display("Invalid RESET_MODE on GP_COUNT14_ADV");
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$finish;
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end
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end
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endcase
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endgenerate
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endmodule
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module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
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input UP, input KEEP, output reg[7:0] POUT);
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parameter RESET_MODE = "RISING";
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parameter RESET_VALUE = "ZERO";
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parameter COUNT_TO = 8'h1;
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parameter CLKIN_DIVIDE = 1;
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reg[7:0] count = COUNT_TO;
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initial begin
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if(CLKIN_DIVIDE != 1) begin
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$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
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$finish;
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end
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end
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//Combinatorially output underflow flag whenever we wrap low
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always @(*) begin
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if(UP)
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OUT = (count == 8'hff);
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else
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OUT = (count == 8'h0);
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POUT = count;
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end
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//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
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//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
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generate
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case(RESET_MODE)
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"RISING": begin
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always @(posedge CLK, posedge RST) begin
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//Resets
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if(RST) begin
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if(RESET_VALUE == "ZERO")
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count <= 0;
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else
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count <= COUNT_TO;
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end
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//Main counter
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else if(KEEP) begin
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end
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else if(UP) begin
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count <= count + 1'd1;
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if(count == 8'hff)
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count <= COUNT_TO;
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end
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else begin
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count <= count - 1'd1;
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if(count == 0)
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count <= COUNT_TO;
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end
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end
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end
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"FALLING": begin
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always @(posedge CLK, negedge RST) begin
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//Resets
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if(!RST) begin
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if(RESET_VALUE == "ZERO")
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count <= 0;
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else
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count <= COUNT_TO;
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end
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//Main counter
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else if(KEEP) begin
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end
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else if(UP) begin
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count <= count + 1'd1;
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if(count == 8'hff)
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count <= COUNT_TO;
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end
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else begin
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count <= count - 1'd1;
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if(count == 0)
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count <= COUNT_TO;
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end
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end
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end
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"BOTH": begin
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initial begin
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$display("Both-edge reset mode for GP_COUNT8_ADV not implemented");
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$finish;
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end
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end
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"LEVEL": begin
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always @(posedge CLK, posedge RST) begin
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//Resets
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if(RST) begin
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if(RESET_VALUE == "ZERO")
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count <= 0;
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else
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count <= COUNT_TO;
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end
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else begin
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if(KEEP) begin
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end
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else if(UP) begin
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count <= count + 1'd1;
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if(count == 8'hff)
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count <= COUNT_TO;
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end
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else begin
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count <= count - 1'd1;
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if(count == 0)
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count <= COUNT_TO;
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end
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end
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end
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end
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default: begin
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initial begin
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$display("Invalid RESET_MODE on GP_COUNT8_ADV");
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$finish;
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end
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end
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endcase
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endgenerate
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endmodule
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module GP_COUNT8(
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input wire CLK,
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input wire RST,
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output reg OUT,
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output reg[7:0] POUT);
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parameter RESET_MODE = "RISING";
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parameter COUNT_TO = 8'h1;
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parameter CLKIN_DIVIDE = 1;
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initial begin
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if(CLKIN_DIVIDE != 1) begin
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$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
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$finish;
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end
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end
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reg[7:0] count = COUNT_TO;
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//Combinatorially output underflow flag whenever we wrap low
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always @(*) begin
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OUT = (count == 8'h0);
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POUT = count;
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end
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//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
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//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
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generate
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case(RESET_MODE)
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"RISING": begin
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always @(posedge CLK, posedge RST) begin
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if(RST)
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count <= 0;
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else begin
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count <= count - 1'd1;
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if(count == 0)
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count <= COUNT_TO;
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end
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end
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end
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"FALLING": begin
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always @(posedge CLK, negedge RST) begin
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if(!RST)
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count <= 0;
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else begin
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count <= count - 1'd1;
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if(count == 0)
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count <= COUNT_TO;
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end
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end
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end
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"BOTH": begin
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initial begin
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$display("Both-edge reset mode for GP_COUNT8 not implemented");
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$finish;
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end
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end
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"LEVEL": begin
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always @(posedge CLK, posedge RST) begin
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if(RST)
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count <= 0;
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else begin
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count <= count - 1'd1;
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if(count == 0)
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count <= COUNT_TO;
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end
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end
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end
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default: begin
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initial begin
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$display("Invalid RESET_MODE on GP_COUNT8");
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$finish;
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end
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end
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endcase
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endgenerate
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endmodule
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module GP_DCMPREF(output reg[7:0]OUT);
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parameter[7:0] REF_VAL = 8'h00;
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initial OUT = REF_VAL;
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endmodule
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module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
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always @(*) begin
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case(SEL)
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2'd00: begin
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OUTA = IN0;
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OUTB = IN3;
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end
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2'd01: begin
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OUTA = IN1;
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OUTB = IN2;
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end
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2'd02: begin
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OUTA = IN2;
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OUTB = IN1;
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end
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2'd03: begin
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OUTA = IN3;
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OUTB = IN0;
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end
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endcase
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end
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endmodule
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module GP_DELAY(input IN, output reg OUT);
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parameter DELAY_STEPS = 1;
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parameter GLITCH_FILTER = 0;
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initial OUT = 0;
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generate
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if(GLITCH_FILTER) begin
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initial begin
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$display("ERROR: GP_DELAY glitch filter mode not implemented");
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$finish;
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end
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end
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//TODO: These delays are PTV dependent! For now, hard code 3v3 timing
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//Change simulation-mode delay depending on global Vdd range (how to specify this?)
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always @(*) begin
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case(DELAY_STEPS)
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1: #166 OUT = IN;
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2: #318 OUT = IN;
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2: #471 OUT = IN;
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3: #622 OUT = IN;
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default: begin
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$display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
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$finish;
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end
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endcase
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end
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endgenerate
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endmodule
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module GP_DFF(input D, CLK, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(posedge CLK) begin
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Q <= D;
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end
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endmodule
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module GP_DFFI(input D, CLK, output reg nQ);
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parameter [0:0] INIT = 1'bx;
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initial nQ = INIT;
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always @(posedge CLK) begin
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nQ <= ~D;
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end
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endmodule
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module GP_DFFR(input D, CLK, nRST, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(posedge CLK, negedge nRST) begin
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if (!nRST)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule
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module GP_DFFRI(input D, CLK, nRST, output reg nQ);
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parameter [0:0] INIT = 1'bx;
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initial nQ = INIT;
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always @(posedge CLK, negedge nRST) begin
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if (!nRST)
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nQ <= 1'b1;
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else
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nQ <= ~D;
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end
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endmodule
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module GP_DFFS(input D, CLK, nSET, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(posedge CLK, negedge nSET) begin
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if (!nSET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule
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module GP_DFFSI(input D, CLK, nSET, output reg nQ);
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parameter [0:0] INIT = 1'bx;
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initial nQ = INIT;
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always @(posedge CLK, negedge nSET) begin
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if (!nSET)
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nQ <= 1'b0;
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else
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nQ <= ~D;
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end
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endmodule
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module GP_DFFSR(input D, CLK, nSR, output reg Q);
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parameter [0:0] INIT = 1'bx;
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parameter [0:0] SRMODE = 1'bx;
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initial Q = INIT;
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always @(posedge CLK, negedge nSR) begin
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if (!nSR)
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Q <= SRMODE;
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else
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Q <= D;
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end
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endmodule
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module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
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parameter [0:0] INIT = 1'bx;
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parameter [0:0] SRMODE = 1'bx;
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initial nQ = INIT;
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always @(posedge CLK, negedge nSR) begin
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if (!nSR)
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nQ <= ~SRMODE;
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else
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nQ <= ~D;
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end
|
|
endmodule
|
|
|
|
module GP_DLATCH(input D, input nCLK, output reg Q);
|
|
parameter [0:0] INIT = 1'bx;
|
|
initial Q = INIT;
|
|
always @(*) begin
|
|
if(!nCLK)
|
|
Q = D;
|
|
end
|
|
endmodule
|
|
|
|
module GP_DLATCHI(input D, input nCLK, output reg nQ);
|
|
parameter [0:0] INIT = 1'bx;
|
|
initial nQ = INIT;
|
|
always @(*) begin
|
|
if(!nCLK)
|
|
nQ = ~D;
|
|
end
|
|
endmodule
|
|
|
|
module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
|
|
parameter [0:0] INIT = 1'bx;
|
|
initial Q = INIT;
|
|
always @(*) begin
|
|
if(!nRST)
|
|
Q = 1'b0;
|
|
else if(!nCLK)
|
|
Q = D;
|
|
end
|
|
endmodule
|
|
|
|
module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
|
|
parameter [0:0] INIT = 1'bx;
|
|
initial nQ = INIT;
|
|
always @(*) begin
|
|
if(!nRST)
|
|
nQ = 1'b1;
|
|
else if(!nCLK)
|
|
nQ = ~D;
|
|
end
|
|
endmodule
|
|
|
|
module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
|
|
parameter [0:0] INIT = 1'bx;
|
|
initial Q = INIT;
|
|
always @(*) begin
|
|
if(!nSET)
|
|
Q = 1'b1;
|
|
else if(!nCLK)
|
|
Q = D;
|
|
end
|
|
endmodule
|
|
|
|
module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
|
|
parameter [0:0] INIT = 1'bx;
|
|
initial nQ = INIT;
|
|
always @(*) begin
|
|
if(!nSET)
|
|
nQ = 1'b0;
|
|
else if(!nCLK)
|
|
nQ = ~D;
|
|
end
|
|
endmodule
|
|
|
|
module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
|
|
parameter [0:0] INIT = 1'bx;
|
|
parameter[0:0] SRMODE = 1'bx;
|
|
initial Q = INIT;
|
|
always @(*) begin
|
|
if(!nSR)
|
|
Q = SRMODE;
|
|
else if(!nCLK)
|
|
Q = D;
|
|
end
|
|
endmodule
|
|
|
|
module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
|
|
parameter [0:0] INIT = 1'bx;
|
|
parameter[0:0] SRMODE = 1'bx;
|
|
initial nQ = INIT;
|
|
always @(*) begin
|
|
if(!nSR)
|
|
nQ = ~SRMODE;
|
|
else if(!nCLK)
|
|
nQ = ~D;
|
|
end
|
|
endmodule
|
|
|
|
module GP_IBUF(input IN, output OUT);
|
|
assign OUT = IN;
|
|
endmodule
|
|
|
|
module GP_IOBUF(input IN, input OE, output OUT, inout IO);
|
|
assign OUT = IO;
|
|
assign IO = OE ? IN : 1'bz;
|
|
endmodule
|
|
|
|
module GP_INV(input IN, output OUT);
|
|
assign OUT = ~IN;
|
|
endmodule
|
|
|
|
module GP_OBUF(input IN, output OUT);
|
|
assign OUT = IN;
|
|
endmodule
|
|
|
|
module GP_OBUFT(input IN, input OE, output OUT);
|
|
assign OUT = OE ? IN : 1'bz;
|
|
endmodule
|
|
|
|
module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
|
|
initial OUT = 0;
|
|
parameter PATTERN_DATA = 16'h0;
|
|
parameter PATTERN_LEN = 5'd16;
|
|
|
|
localparam COUNT_MAX = PATTERN_LEN - 1'h1;
|
|
|
|
reg[3:0] count = 0;
|
|
always @(posedge CLK, negedge nRST) begin
|
|
|
|
if(!nRST)
|
|
count <= 0;
|
|
|
|
else begin
|
|
count <= count - 1'h1;
|
|
if(count == 0)
|
|
count <= COUNT_MAX;
|
|
end
|
|
end
|
|
|
|
always @(*)
|
|
OUT = PATTERN_DATA[count];
|
|
|
|
endmodule
|
|
|
|
module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
|
|
|
|
parameter OUTA_TAP = 1;
|
|
parameter OUTA_INVERT = 0;
|
|
parameter OUTB_TAP = 1;
|
|
|
|
reg[15:0] shreg = 0;
|
|
|
|
always @(posedge CLK, negedge nRST) begin
|
|
|
|
if(!nRST)
|
|
shreg = 0;
|
|
|
|
else
|
|
shreg <= {shreg[14:0], IN};
|
|
|
|
end
|
|
|
|
assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
|
|
assign OUTB = shreg[OUTB_TAP - 1];
|
|
|
|
endmodule
|
|
|
|
module GP_VDD(output OUT);
|
|
assign OUT = 1;
|
|
endmodule
|
|
|
|
module GP_VSS(output OUT);
|
|
assign OUT = 0;
|
|
endmodule
|