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yosys/tests
2023-08-11 04:46:52 +02:00
..
aiger
arch Update tests 2023-06-09 14:41:45 +02:00
asicworld
bind
blif Adding check for BLIF names command input plane size. 2022-08-21 23:18:20 -05:00
bram Fix the tests we just broke 2021-12-10 00:22:37 +01:00
errors
fsm
hana
liberty fix file rights 2023-05-17 13:39:57 +02:00
lut
memfile
memlib More tests in memlib/generate.py 2023-02-21 05:23:15 +13:00
memories Fix the tests we just broke 2021-12-10 00:22:37 +01:00
opt opt_expr: Fix 'signed X>=0' replacement for wide output ports 2023-08-01 13:50:12 +01:00
opt_share
proc proc_rom: Add special handling of const-0 address bits. 2022-05-18 17:32:30 +02:00
realmath
rpc
sat Proper example code 2022-03-14 15:39:11 +01:00
select
share
sim Replace GNU specific invocation of basename(1) with the equivalent 2022-10-23 11:02:18 +13:00
simple verilog: Support module-scoped task/function calls 2022-10-29 15:14:11 -04:00
simple_abc9
smv
sva verific: Use new value change logic also for $stable of wide signals. 2022-05-11 13:05:27 +02:00
svinterfaces Resolve package types in interfaces (#3658) 2023-02-12 18:25:39 -05:00
svtypes Corrected handling of nested typedefs of struct/union 2023-07-20 23:39:44 -04:00
techmap tests: Extend aigmap.ys with SAT comparison 2023-07-31 16:26:50 +02:00
tools support file locations containing spaces 2022-08-08 20:30:50 +02:00
unit
various ast: use new format string helpers. 2023-08-11 04:46:52 +02:00
verific verific: Fix enum_values support and signed attribute values 2023-03-15 09:51:36 +01:00
verilog Standard compliance for tests/verilog/block_labels.ys 2023-05-21 16:38:14 -04:00
vloghtb
xprop xprop tests: Make iverilog invocation more portable 2023-02-13 16:54:11 +01:00
gen-tests-makefile.sh Out of bounds checking for struct/union members 2023-02-19 23:25:08 +01:00