yosys/tests/verilog/unbased_unsized.ys at 3f69a768f4aac3e1b95f830b13c866e20a0f073e - mirrors/yosys - Libre-Chip.org

mirrors/yosys

mirror of https://github.com/YosysHQ/yosys synced 2025-09-12 12:41:28 +00:00

George Rennie 8fb3f88842 tests: remove -seq 1 from sat with -tempinduct where possible

* When used with -tempinduct mode, -seq <N> causes assertions to be
  ignored in the first N steps. While this has uses for reset modelling,
  for these test cases it is unnecessary and could lead to failures
  slipping through uncaught

2025-09-08 18:04:32 +02:00

8 lines

148 B

Text

Raw Blame History

 read_verilog -sv unbased_unsized.sv
 hierarchy
 proc
 flatten
 opt -full
 async2sync
 select -module top
 sat -verify -tempinduct -prove-asserts -show-all