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87 lines
2 KiB
Text
87 lines
2 KiB
Text
# https://github.com/YosysHQ/yosys/issues/964
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read_verilog -formal <<EOT
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module mux_index_8_2 #(parameter N=8, parameter W=2) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
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assign o = i[s*W+:W];
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endmodule
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EOT
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prep
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design -save gold
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opt
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peepopt
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techmap
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opt
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muxcover -mux8
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clean
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opt_expr -mux_bool
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select -assert-count 2 t:$_MUX8_
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select -assert-none t:$_MUX_ t:$_MUX4_ t:$_MUX16_
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select -assert-none t:$_AND_ t:$_OR_ t:$_XOR_ t:$_NAND_ t:$_NOR_ t:$_XNOR_
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techmap -map +/simcells.v t:$_MUX8_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts miter
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design -reset
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read_verilog -formal <<EOT
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module mux_index_8_3 #(parameter N=8, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
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assign o = i[s*W+:W];
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endmodule
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EOT
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prep
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design -save gold
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opt
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peepopt
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techmap
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opt
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muxcover -mux8
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clean
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opt_expr -mux_bool
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select -assert-count 3 t:$_MUX8_
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select -assert-none t:$_MUX_ t:$_MUX4_ t:$_MUX16_
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select -assert-none t:$_AND_ t:$_OR_ t:$_XOR_ t:$_NAND_ t:$_NOR_ t:$_XNOR_
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techmap -map +/simcells.v t:$_MUX8_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts miter
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design -reset
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read_verilog -formal <<EOT
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module mux_index_8_4 #(parameter N=8, parameter W=4) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
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assign o = i[s*W+:W];
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endmodule
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EOT
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prep
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design -save gold
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opt
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peepopt
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techmap
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opt
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muxcover -mux8
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clean
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opt_expr -mux_bool
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select -assert-count 4 t:$_MUX8_
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select -assert-none t:$_MUX_ t:$_MUX4_ t:$_MUX16_
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select -assert-none t:$_AND_ t:$_OR_ t:$_XOR_ t:$_NAND_ t:$_NOR_ t:$_XNOR_
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techmap -map +/simcells.v t:$_MUX8_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts miter
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