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yosys/tests/opt/opt_merge_properties.ys
Miodrag Milanovic 48a3dcc02a End of file fix
2026-06-23 07:23:41 +02:00

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read_verilog -sv <<EOF
module top ();
always_comb begin
label1: cover(0);
label2: cover(0);
end
endmodule
EOF
hierarchy -top top
proc
chformal -lower
clean
opt_merge
select -assert-count 2 t:$cover