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12 lines
327 B
Text
12 lines
327 B
Text
read_verilog <<EOT
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module top(input [24:0] a, input [17:0] b, output [42:0] o1, o2, o5);
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DSP48E1 m1 (.A(a), .B(16'd1234), .P(o1));
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assign o2 = a * 16'd0;
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wire [42:0] o3, o4;
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DSP48E1 m2 (.A(a), .B(b), .P(o3));
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assign o4 = a * b;
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DSP48E1 m3 (.A(a), .B(b), .P(o5));
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endmodule
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EOT
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read_verilog -lib +/xilinx/cells_sim.v
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xilinx_dsp
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