mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 19:52:31 +00:00
e0ae7b7af4
There are some leftovers, but this is an easy regex-based approach that removes most of them.
99 lines
3 KiB
C++
99 lines
3 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/log_help.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct PortlistPass : public Pass {
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PortlistPass() : Pass("portlist", "list (top-level) ports") { }
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bool formatted_help() override {
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auto *help = PrettyHelp::get_current();
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help->set_group("passes/status");
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return false;
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}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" portlist [options] [selection]\n");
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log("\n");
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log("This command lists all module ports found in the selected modules.\n");
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log("\n");
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log("If no selection is provided then it lists the ports on the top module.\n");
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log("\n");
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log(" -m\n");
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log(" print verilog blackbox module definitions instead of port lists\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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bool m_mode = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-m") {
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m_mode = true;
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continue;
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}
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break;
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}
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bool first_module = true;
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auto handle_module = [&](RTLIL::Module *module) {
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vector<string> ports;
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if (first_module)
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first_module = false;
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else
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log("\n");
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for (auto port : module->ports) {
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auto *w = module->wire(port);
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ports.push_back(stringf("%s [%d:%d] %s", w->port_input ? w->port_output ? "inout" : "input" : "output",
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w->upto ? w->start_offset : w->start_offset + w->width - 1,
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w->upto ? w->start_offset + w->width - 1 : w->start_offset,
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log_id(w)));
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}
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log("module %s%s\n", log_id(module), m_mode ? " (" : "");
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for (int i = 0; i < GetSize(ports); i++)
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log("%s%s\n", ports[i], m_mode && i+1 < GetSize(ports) ? "," : "");
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if (m_mode)
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log(");\nendmodule\n");
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};
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if (argidx == args.size())
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{
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auto *top = design->top_module();
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if (top == nullptr)
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log_cmd_error("Can't find top module in current design!\n");
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handle_module(top);
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}
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else
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{
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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handle_module(module);
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}
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}
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} PortlistPass;
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PRIVATE_NAMESPACE_END
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