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13 lines
333 B
Plaintext
13 lines
333 B
Plaintext
design -reset
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read_verilog <<EOF
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module top(input clk, input a, input b, output [9:0] x);
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wire [9:0] ripple;
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reg [9:0] prev_ripple = 9'b0;
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always @(posedge clk) prev_ripple <= ripple;
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assign ripple = {ripple[8:0], a} ^ prev_ripple; // only cyclic at the coarse-grain level
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assign x = ripple[9] + b;
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endmodule
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EOF
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check -assert
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