| .. |
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abc9_map.v
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intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY
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2020-07-04 19:45:10 +02:00 |
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abc9_model.v
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intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF
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2020-07-04 19:45:10 +02:00 |
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abc9_unmap.v
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intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY
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2020-07-04 19:45:10 +02:00 |
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alm_map.v
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Add force_downto and force_upto wire attributes.
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2020-05-19 01:42:40 +02:00 |
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alm_sim.v
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intel_alm: preliminary Arria V support
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2021-11-25 17:20:36 +01:00 |
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arith_alm_map.v
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intel_alm: Fix illegal carry chains
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2021-05-15 22:37:06 +01:00 |
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bram_m10k.txt
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intel_alm: M10K write-enable is negative-true
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2022-03-09 20:18:06 +00:00 |
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bram_m10k_map.v
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intel_alm: M10K write-enable is negative-true
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2022-03-09 20:18:06 +00:00 |
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bram_m20k.txt
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synth_intel_alm: alternative synthesis for Intel FPGAs
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2020-04-15 11:40:41 +02:00 |
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bram_m20k_map.v
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Fix files with CRLF line endings
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2021-06-09 12:16:33 +02:00 |
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dff_map.v
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synth_intel_alm: Use dfflegalize.
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2020-07-04 22:56:16 +02:00 |
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dff_sim.v
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intel_alm: preliminary Arria V support
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2021-11-25 17:20:36 +01:00 |
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dsp_map.v
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intel_alm: Add multiply signedness to cells
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2020-08-26 22:50:16 +02:00 |
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dsp_sim.v
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intel_alm: preliminary Arria V support
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2021-11-25 17:20:36 +01:00 |
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lutram_mlab.txt
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intel_alm: direct LUTRAM cell instantiation
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2020-05-07 21:03:13 +02:00 |
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megafunction_bb.v
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CycloneV: Add (passthrough) support for cyclonev_oscillator
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2021-10-17 20:00:03 +02:00 |
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mem_sim.v
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intel_alm: M10K write-enable is negative-true
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2022-03-09 20:18:06 +00:00 |
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misc_sim.v
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intel_alm: Add global buffer insertion
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2021-05-15 22:37:06 +01:00 |
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quartus_rename.v
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intel_alm: M10K write-enable is negative-true
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2022-03-09 20:18:06 +00:00 |
