mirror of
https://github.com/YosysHQ/yosys
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5c77c73888
This does not yet seem to work completely as intended. The idea is to trim the port widths of the extracted circuits, so that it does not leave X bits as padding at the MSBs.
810 lines
29 KiB
C++
810 lines
29 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include "libs/subcircuit/subcircuit.h"
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#include <algorithm>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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class SubCircuitSolver : public SubCircuit::Solver
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{
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public:
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bool ignore_parameters;
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std::set<std::pair<RTLIL::IdString, RTLIL::IdString>> ignored_parameters;
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std::set<RTLIL::IdString> cell_attr, wire_attr;
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SubCircuitSolver() : ignore_parameters(false)
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{
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}
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bool compareAttributes(const std::set<RTLIL::IdString> &attr, const dict<RTLIL::IdString, RTLIL::Const> &needleAttr, const dict<RTLIL::IdString, RTLIL::Const> &haystackAttr)
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{
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for (auto &it : attr) {
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size_t nc = needleAttr.count(it), hc = haystackAttr.count(it);
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if (nc != hc || (nc > 0 && needleAttr.at(it) != haystackAttr.at(it)))
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return false;
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}
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return true;
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}
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RTLIL::Const unified_param(RTLIL::IdString cell_type, RTLIL::IdString param, RTLIL::Const value)
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{
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if (!cell_type.begins_with("$") || cell_type.begins_with("$_"))
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return value;
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#define param_bool(_n) if (param == _n) return value.as_bool();
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param_bool(ID::ARST_POLARITY);
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param_bool(ID::A_SIGNED);
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param_bool(ID::B_SIGNED);
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param_bool(ID::CLK_ENABLE);
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param_bool(ID::CLK_POLARITY);
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param_bool(ID::CLR_POLARITY);
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param_bool(ID::EN_POLARITY);
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param_bool(ID::SET_POLARITY);
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param_bool(ID::TRANSPARENT);
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#undef param_bool
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#define param_int(_n) if (param == _n) return value.as_int();
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param_int(ID::ABITS)
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param_int(ID::A_WIDTH)
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param_int(ID::B_WIDTH)
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param_int(ID::CTRL_IN_WIDTH)
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param_int(ID::CTRL_OUT_WIDTH)
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param_int(ID::OFFSET)
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param_int(ID::PORTID)
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param_int(ID::PRIORITY)
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param_int(ID::RD_PORTS)
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param_int(ID::SIZE)
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param_int(ID::STATE_BITS)
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param_int(ID::STATE_NUM)
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param_int(ID::STATE_NUM_LOG2)
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param_int(ID::STATE_RST)
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param_int(ID::S_WIDTH)
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param_int(ID::TRANS_NUM)
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param_int(ID::WIDTH)
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param_int(ID::WR_PORTS)
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param_int(ID::Y_WIDTH)
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#undef param_int
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return value;
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}
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virtual bool userCompareNodes(const std::string &, const std::string &, void *needleUserData,
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const std::string &, const std::string &, void *haystackUserData, const std::map<std::string, std::string> &portMapping)
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{
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RTLIL::Cell *needleCell = (RTLIL::Cell*) needleUserData;
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RTLIL::Cell *haystackCell = (RTLIL::Cell*) haystackUserData;
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if (!needleCell || !haystackCell) {
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log_assert(!needleCell && !haystackCell);
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return true;
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}
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// TODO: add an optional check to make sure the port-assignment is in one continous block, not in chunks
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if (!ignore_parameters) {
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std::map<RTLIL::IdString, RTLIL::Const> needle_param, haystack_param;
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for (auto &it : needleCell->parameters)
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if (!ignored_parameters.count(std::pair<RTLIL::IdString, RTLIL::IdString>(needleCell->type, it.first)))
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needle_param[it.first] = unified_param(needleCell->type, it.first, it.second);
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for (auto &it : haystackCell->parameters)
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if (!ignored_parameters.count(std::pair<RTLIL::IdString, RTLIL::IdString>(haystackCell->type, it.first)))
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haystack_param[it.first] = unified_param(haystackCell->type, it.first, it.second);
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if (needle_param != haystack_param)
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return false;
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}
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if (cell_attr.size() > 0 && !compareAttributes(cell_attr, needleCell->attributes, haystackCell->attributes))
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return false;
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if (wire_attr.size() > 0)
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{
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RTLIL::Wire *lastNeedleWire = nullptr;
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RTLIL::Wire *lastHaystackWire = nullptr;
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dict<RTLIL::IdString, RTLIL::Const> emptyAttr;
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for (auto &conn : needleCell->connections())
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{
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RTLIL::SigSpec needleSig = conn.second;
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RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first.str()));
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for (int i = 0; i < min(needleSig.size(), haystackSig.size()); i++) {
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RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire;
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if (needleWire != lastNeedleWire || haystackWire != lastHaystackWire)
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if (!compareAttributes(wire_attr, needleWire ? needleWire->attributes : emptyAttr, haystackWire ? haystackWire->attributes : emptyAttr))
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return false;
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lastNeedleWire = needleWire, lastHaystackWire = haystackWire;
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}
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}
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}
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return true;
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}
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};
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struct bit_ref_t {
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std::string cell, port;
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int bit;
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};
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bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports, int min_port_width = -1, RTLIL::Design *sel = nullptr,
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int max_fanout = -1, std::set<std::pair<RTLIL::IdString, RTLIL::IdString>> *split = nullptr)
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{
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SigMap sigmap(mod);
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std::map<RTLIL::SigBit, bit_ref_t> sig_bit_ref;
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if (sel && !sel->selected(mod)) {
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log(" Skipping module %s as it is not selected.\n", log_id(mod->name));
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return false;
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}
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if (mod->processes.size() > 0) {
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log(" Skipping module %s as it contains unprocessed processes.\n", log_id(mod->name));
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return false;
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}
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if (constports) {
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graph.createNode("$const$0", "$const$0", nullptr, true);
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graph.createNode("$const$1", "$const$1", nullptr, true);
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graph.createNode("$const$x", "$const$x", nullptr, true);
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graph.createNode("$const$z", "$const$z", nullptr, true);
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graph.createPort("$const$0", "\\Y", 1);
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graph.createPort("$const$1", "\\Y", 1);
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graph.createPort("$const$x", "\\Y", 1);
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graph.createPort("$const$z", "\\Y", 1);
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graph.markExtern("$const$0", "\\Y", 0);
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graph.markExtern("$const$1", "\\Y", 0);
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graph.markExtern("$const$x", "\\Y", 0);
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graph.markExtern("$const$z", "\\Y", 0);
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}
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std::map<std::pair<RTLIL::Wire*, int>, int> sig_use_count;
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if (max_fanout > 0)
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for (auto cell : mod->cells())
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{
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if (!sel || sel->selected(mod, cell))
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for (auto &conn : cell->connections()) {
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RTLIL::SigSpec conn_sig = conn.second;
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sigmap.apply(conn_sig);
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for (auto &bit : conn_sig)
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if (bit.wire != nullptr)
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sig_use_count[std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset)]++;
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}
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}
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// create graph nodes from cells
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for (auto cell : mod->cells())
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{
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if (sel && !sel->selected(mod, cell))
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continue;
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std::string type = cell->type.str();
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if (sel == nullptr && type.compare(0, 2, "\\$") == 0)
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type = type.substr(1);
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graph.createNode(cell->name.str(), type, (void*)cell);
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for (auto &conn : cell->connections())
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{
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graph.createPort(cell->name.str(), conn.first.str(), conn.second.size(), min_port_width);
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if (split && split->count(std::pair<RTLIL::IdString, RTLIL::IdString>(cell->type, conn.first)) > 0)
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continue;
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RTLIL::SigSpec conn_sig = conn.second;
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sigmap.apply(conn_sig);
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for (int i = 0; i < conn_sig.size(); i++)
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{
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auto &bit = conn_sig[i];
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if (bit.wire == nullptr) {
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if (constports) {
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std::string node = "$const$x";
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if (bit == RTLIL::State::S0) node = "$const$0";
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if (bit == RTLIL::State::S1) node = "$const$1";
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if (bit == RTLIL::State::Sz) node = "$const$z";
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graph.createConnection(cell->name.str(), conn.first.str(), i, node, "\\Y", 0);
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} else
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graph.createConstant(cell->name.str(), conn.first.str(), i, int(bit.data));
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continue;
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}
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if (max_fanout > 0 && sig_use_count[std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset)] > max_fanout)
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continue;
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if (sel && !sel->selected(mod, bit.wire))
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continue;
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if (sig_bit_ref.count(bit) == 0) {
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bit_ref_t &bit_ref = sig_bit_ref[bit];
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bit_ref.cell = cell->name.str();
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bit_ref.port = conn.first.str();
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bit_ref.bit = i;
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}
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bit_ref_t &bit_ref = sig_bit_ref[bit];
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graph.createConnection(bit_ref.cell, bit_ref.port, bit_ref.bit, cell->name.str(), conn.first.str(), i);
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}
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}
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}
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// mark external signals (used in non-selected cells)
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for (auto cell : mod->cells())
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{
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if (sel && !sel->selected(mod, cell))
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for (auto &conn : cell->connections())
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{
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RTLIL::SigSpec conn_sig = conn.second;
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sigmap.apply(conn_sig);
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for (auto &bit : conn_sig)
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if (sig_bit_ref.count(bit) != 0) {
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bit_ref_t &bit_ref = sig_bit_ref[bit];
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graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit);
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}
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}
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}
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// mark external signals (used in module ports)
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for (auto wire : mod->wires())
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{
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if (wire->port_id > 0)
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{
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RTLIL::SigSpec conn_sig(wire);
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sigmap.apply(conn_sig);
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for (auto &bit : conn_sig)
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if (sig_bit_ref.count(bit) != 0) {
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bit_ref_t &bit_ref = sig_bit_ref[bit];
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graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit);
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}
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}
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}
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// graph.print();
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return true;
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}
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RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit::Solver::Result &match, bool minimize_port_width=false)
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{
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SigMap sigmap(needle);
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SigSet<std::pair<RTLIL::IdString, int>> sig2port;
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// create new cell
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RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), autoidx++), needle->name);
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// create cell ports
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for (auto wire : needle->wires()) {
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// for all ports in the needle module
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if (wire->port_id > 0) {
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cell->setPort(wire->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width));
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// remember all bits
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for (int i = 0; i < wire->width; i++)
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sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<RTLIL::IdString, int>(wire->name, i));
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}
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}
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// delete replaced cells and connect new ports
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for (auto &it : match.mappings)
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{
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auto &mapping = it.second;
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RTLIL::Cell *needle_cell = (RTLIL::Cell*)mapping.needleUserData;
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RTLIL::Cell *haystack_cell = (RTLIL::Cell*)mapping.haystackUserData;
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if (needle_cell == nullptr)
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continue;
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for (auto &conn : needle_cell->connections()) {
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RTLIL::SigSpec nsig = sigmap(conn.second);
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std::string nsig_name = conn.first.str();
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// if it is a mapped port and connects to a wire/port in the needle module
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if (mapping.portMapping.count(nsig_name) > 0 && sig2port.has(sigmap(nsig))) {
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RTLIL::IdString hport_name = mapping.portMapping[nsig_name];
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// copy signed-ness from haystack to new needle cell
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RTLIL::IdString nconn_sgn = RTLIL::escape_id(nsig_name + "_SIGNED");
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if(haystack_cell->hasParam(RTLIL::escape_id(hport_name.str() + "_SIGNED"))) {
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cell->setParam(nconn_sgn, haystack_cell->getParam(RTLIL::escape_id(hport_name.str() + "_SIGNED")));
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} else {
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cell->setParam(nconn_sgn, 0);
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}
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// add and connect ports
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RTLIL::SigSpec hsig = haystack_cell->getPort(hport_name);
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for (int i = 0; i < nsig.size() && i < hsig.size(); i++) { // for each bit
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// for each needle port connected to wire-bit
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for (auto &port : sig2port.find(nsig[i])) {
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RTLIL::SigSpec bitsig = hsig.extract(i, 1);
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RTLIL::SigSpec new_sig = cell->getPort(port.first);
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new_sig.replace(port.second, bitsig);
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cell->setPort(port.first, new_sig);
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}
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}
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}
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}
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haystack->remove(haystack_cell);
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}
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// for all connections/port of the new cell
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for (auto &conn : cell->connections()) {
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// for all ports in the needle module
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RTLIL::IdString port_name = conn.first;
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RTLIL::SigSpec port = cell->getPort(conn.first);
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if(minimize_port_width) {
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// starting from the MSB, remove until first non-constant bit
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int msb = port.size()-1;
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for (; msb >= 0; msb--) {
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if(port[msb].is_wire())
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break;
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}
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if(msb > 0 && msb < port.size()-1) {
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log("removing in %s (width: %d) from bit %d-%d\n", port_name.c_str(), port.size(), port.size()-1, msb+1);
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log(" remove(%d, %d)\n", msb+1, port.size()-1-msb);
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port.remove(msb+1, port.size()-1-msb);
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log("removing in %s (width: %d) from bit %d-%d\n", port_name.c_str(), port.size(), port.size()-1, msb+1);
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}
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}
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RTLIL::IdString port_width = RTLIL::escape_id(port_name.str() + "_WIDTH");
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cell->setParam(port_width, port.size());
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}
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return cell;
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}
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bool compareSortNeedleList(RTLIL::Module *left, RTLIL::Module *right)
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{
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int left_idx = 0, right_idx = 0;
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if (left->attributes.count(ID::extract_order) > 0)
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left_idx = left->attributes.at(ID::extract_order).as_int();
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if (right->attributes.count(ID::extract_order) > 0)
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right_idx = right->attributes.at(ID::extract_order).as_int();
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if (left_idx != right_idx)
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return left_idx < right_idx;
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return left->name < right->name;
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}
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struct ExtractPass : public Pass {
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ExtractPass() : Pass("extract", "find subcircuits and replace them with cells") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" extract -map <map_file> [options] [selection]\n");
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log(" extract -mine <out_file> [options] [selection]\n");
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log("\n");
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log("This pass looks for subcircuits that are isomorphic to any of the modules\n");
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log("in the given map file and replaces them with instances of this modules. The\n");
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log("map file can be a Verilog source file (*.v) or an RTLIL source file (*.il).\n");
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log("\n");
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log(" -map <map_file>\n");
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log(" use the modules in this file as reference. This option can be used\n");
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log(" multiple times.\n");
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log("\n");
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log(" -map %%<design-name>\n");
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log(" use the modules in this in-memory design as reference. This option can\n");
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log(" be used multiple times.\n");
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log("\n");
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log(" -verbose\n");
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log(" print debug output while analyzing\n");
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log("\n");
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log(" -constports\n");
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log(" also find instances with constant drivers. this may be much\n");
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log(" slower than the normal operation.\n");
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log("\n");
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log(" -nodefaultswaps\n");
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log(" normally builtin port swapping rules for internal cells are used per\n");
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log(" default. This turns that off, so e.g. 'a^b' does not match 'b^a'\n");
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log(" when this option is used.\n");
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log("\n");
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log(" -compat <needle_type> <haystack_type>\n");
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log(" Per default, the cells in the map file (needle) must have the\n");
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log(" type as the cells in the active design (haystack). This option\n");
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log(" can be used to register additional pairs of types that should\n");
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log(" match. This option can be used multiple times.\n");
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log("\n");
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log(" -swap <needle_type> <port1>,<port2>[,...]\n");
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log(" Register a set of swappable ports for a needle cell type.\n");
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log(" This option can be used multiple times.\n");
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log("\n");
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log(" -perm <needle_type> <port1>,<port2>[,...] <portA>,<portB>[,...]\n");
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log(" Register a valid permutation of swappable ports for a needle\n");
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|
log(" cell type. This option can be used multiple times.\n");
|
|
log("\n");
|
|
log(" -cell_attr <attribute_name>\n");
|
|
log(" Attributes on cells with the given name must match.\n");
|
|
log("\n");
|
|
log(" -wire_attr <attribute_name>\n");
|
|
log(" Attributes on wires with the given name must match.\n");
|
|
log("\n");
|
|
log(" -ignore_parameters\n");
|
|
log(" Do not use parameters when matching cells.\n");
|
|
log("\n");
|
|
log(" -ignore_param <cell_type> <parameter_name>\n");
|
|
log(" Do not use this parameter when matching cells.\n");
|
|
log("\n");
|
|
log("This pass does not operate on modules with unprocessed processes in it.\n");
|
|
log("(I.e. the 'proc' pass should be used first to convert processes to netlists.)\n");
|
|
log("\n");
|
|
log("This pass can also be used for mining for frequent subcircuits. In this mode\n");
|
|
log("the following options are to be used instead of the -map option.\n");
|
|
log("\n");
|
|
log(" -mine <out_file>\n");
|
|
log(" mine for frequent subcircuits and write them to the given RTLIL file\n");
|
|
log("\n");
|
|
log(" -mine_cells_span <min> <max>\n");
|
|
log(" only mine for subcircuits with the specified number of cells\n");
|
|
log(" default value: 3 5\n");
|
|
log("\n");
|
|
log(" -mine_min_freq <num>\n");
|
|
log(" only mine for subcircuits with at least the specified number of matches\n");
|
|
log(" default value: 10\n");
|
|
log("\n");
|
|
log(" -mine_limit_matches_per_module <num>\n");
|
|
log(" when calculating the number of matches for a subcircuit, don't count\n");
|
|
log(" more than the specified number of matches per module\n");
|
|
log("\n");
|
|
log(" -mine_max_fanout <num>\n");
|
|
log(" don't consider internal signals with more than <num> connections\n");
|
|
log("\n");
|
|
log(" -min_port_width <num>\n");
|
|
log(" match all subcircuits with port widths starting from <num>");
|
|
log(" up to the needle port width defined in the map-design\n");
|
|
log(" default: -1 (exact port width matching)\n");
|
|
log("\n");
|
|
log("The modules in the map file may have the attribute 'extract_order' set to an\n");
|
|
log("integer value. Then this value is used to determine the order in which the pass\n");
|
|
log("tries to map the modules to the design (ascending, default value is 0).\n");
|
|
log("\n");
|
|
log("See 'help techmap' for a pass that does the opposite thing.\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
|
{
|
|
log_header(design, "Executing EXTRACT pass (map subcircuits to cells).\n");
|
|
log_push();
|
|
|
|
SubCircuitSolver solver;
|
|
|
|
std::vector<std::string> map_filenames;
|
|
std::string mine_outfile;
|
|
bool constports = false;
|
|
bool nodefaultswaps = false;
|
|
|
|
bool mine_mode = false;
|
|
int mine_cells_min = 3;
|
|
int mine_cells_max = 5;
|
|
int mine_min_freq = 10;
|
|
int mine_limit_mod = -1;
|
|
int mine_max_fanout = -1;
|
|
int min_port_width = -1;
|
|
std::set<std::pair<RTLIL::IdString, RTLIL::IdString>> mine_split;
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
|
if (args[argidx] == "-map" && argidx+1 < args.size()) {
|
|
if (mine_mode)
|
|
log_cmd_error("You cannot mix -map and -mine.\n");
|
|
map_filenames.push_back(args[++argidx]);
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-mine" && argidx+1 < args.size()) {
|
|
if (!map_filenames.empty())
|
|
log_cmd_error("You cannot mix -map and -mine.\n");
|
|
mine_outfile = args[++argidx];
|
|
mine_mode = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-mine_cells_span" && argidx+2 < args.size()) {
|
|
mine_cells_min = atoi(args[++argidx].c_str());
|
|
mine_cells_max = atoi(args[++argidx].c_str());
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-mine_min_freq" && argidx+1 < args.size()) {
|
|
mine_min_freq = atoi(args[++argidx].c_str());
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-mine_limit_matches_per_module" && argidx+1 < args.size()) {
|
|
mine_limit_mod = atoi(args[++argidx].c_str());
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-mine_split" && argidx+2 < args.size()) {
|
|
mine_split.insert(std::pair<RTLIL::IdString, RTLIL::IdString>(RTLIL::escape_id(args[argidx+1]), RTLIL::escape_id(args[argidx+2])));
|
|
argidx += 2;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-mine_max_fanout" && argidx+1 < args.size()) {
|
|
mine_max_fanout = atoi(args[++argidx].c_str());
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-verbose") {
|
|
solver.setVerbose();
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-constports") {
|
|
constports = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-nodefaultswaps") {
|
|
nodefaultswaps = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-compat" && argidx+2 < args.size()) {
|
|
std::string needle_type = RTLIL::escape_id(args[++argidx]);
|
|
std::string haystack_type = RTLIL::escape_id(args[++argidx]);
|
|
solver.addCompatibleTypes(needle_type, haystack_type);
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-swap" && argidx+2 < args.size()) {
|
|
std::string type = RTLIL::escape_id(args[++argidx]);
|
|
std::set<std::string> ports;
|
|
std::string ports_str = args[++argidx], p;
|
|
while (!(p = next_token(ports_str, ",\t\r\n ")).empty())
|
|
ports.insert(RTLIL::escape_id(p));
|
|
solver.addSwappablePorts(type, ports);
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-perm" && argidx+3 < args.size()) {
|
|
std::string type = RTLIL::escape_id(args[++argidx]);
|
|
std::vector<std::string> map_left, map_right;
|
|
std::string left_str = args[++argidx];
|
|
std::string right_str = args[++argidx], p;
|
|
while (!(p = next_token(left_str, ",\t\r\n ")).empty())
|
|
map_left.push_back(RTLIL::escape_id(p));
|
|
while (!(p = next_token(right_str, ",\t\r\n ")).empty())
|
|
map_right.push_back(RTLIL::escape_id(p));
|
|
if (map_left.size() != map_right.size())
|
|
log_cmd_error("Arguments to -perm are not a valid permutation!\n");
|
|
std::map<std::string, std::string> map;
|
|
for (size_t i = 0; i < map_left.size(); i++)
|
|
map[map_left[i]] = map_right[i];
|
|
std::sort(map_left.begin(), map_left.end());
|
|
std::sort(map_right.begin(), map_right.end());
|
|
if (map_left != map_right)
|
|
log_cmd_error("Arguments to -perm are not a valid permutation!\n");
|
|
solver.addSwappablePortsPermutation(type, map);
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-cell_attr" && argidx+1 < args.size()) {
|
|
solver.cell_attr.insert(RTLIL::escape_id(args[++argidx]));
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-wire_attr" && argidx+1 < args.size()) {
|
|
solver.wire_attr.insert(RTLIL::escape_id(args[++argidx]));
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-ignore_parameters") {
|
|
solver.ignore_parameters = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-ignore_param" && argidx+2 < args.size()) {
|
|
solver.ignored_parameters.insert(std::pair<RTLIL::IdString, RTLIL::IdString>(RTLIL::escape_id(args[argidx+1]), RTLIL::escape_id(args[argidx+2])));
|
|
argidx += 2;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-min_port_width" && argidx+1 < args.size()) {
|
|
min_port_width = atoi(args[++argidx].c_str());
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(args, argidx, design);
|
|
|
|
if (!nodefaultswaps) {
|
|
solver.addSwappablePorts("$and", "\\A", "\\B");
|
|
solver.addSwappablePorts("$or", "\\A", "\\B");
|
|
solver.addSwappablePorts("$xor", "\\A", "\\B");
|
|
solver.addSwappablePorts("$xnor", "\\A", "\\B");
|
|
solver.addSwappablePorts("$eq", "\\A", "\\B");
|
|
solver.addSwappablePorts("$ne", "\\A", "\\B");
|
|
solver.addSwappablePorts("$eqx", "\\A", "\\B");
|
|
solver.addSwappablePorts("$nex", "\\A", "\\B");
|
|
solver.addSwappablePorts("$add", "\\A", "\\B");
|
|
solver.addSwappablePorts("$mul", "\\A", "\\B");
|
|
solver.addSwappablePorts("$logic_and", "\\A", "\\B");
|
|
solver.addSwappablePorts("$logic_or", "\\A", "\\B");
|
|
solver.addSwappablePorts("$_AND_", "\\A", "\\B");
|
|
solver.addSwappablePorts("$_OR_", "\\A", "\\B");
|
|
solver.addSwappablePorts("$_XOR_", "\\A", "\\B");
|
|
}
|
|
|
|
if (map_filenames.empty() && mine_outfile.empty())
|
|
log_cmd_error("Missing option -map <verilog_or_rtlil_file> or -mine <output_rtlil_file>.\n");
|
|
|
|
RTLIL::Design *map = nullptr;
|
|
|
|
if (!mine_mode)
|
|
{
|
|
map = new RTLIL::Design;
|
|
for (auto &filename : map_filenames)
|
|
{
|
|
if (filename.compare(0, 1, "%") == 0)
|
|
{
|
|
if (!saved_designs.count(filename.substr(1))) {
|
|
delete map;
|
|
log_cmd_error("Can't saved design `%s'.\n", filename.c_str()+1);
|
|
}
|
|
for (auto mod : saved_designs.at(filename.substr(1))->modules())
|
|
if (!map->has(mod->name))
|
|
map->add(mod->clone());
|
|
}
|
|
else
|
|
{
|
|
std::ifstream f;
|
|
rewrite_filename(filename);
|
|
f.open(filename.c_str());
|
|
if (f.fail()) {
|
|
delete map;
|
|
log_cmd_error("Can't open map file `%s'.\n", filename.c_str());
|
|
}
|
|
Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog"));
|
|
f.close();
|
|
|
|
if (filename.size() <= 3 || filename.compare(filename.size()-3, std::string::npos, ".il") != 0) {
|
|
Pass::call(map, "proc");
|
|
Pass::call(map, "opt_clean");
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
std::map<std::string, RTLIL::Module*> needle_map, haystack_map;
|
|
std::vector<RTLIL::Module*> needle_list;
|
|
|
|
log_header(design, "Creating graphs for SubCircuit library.\n");
|
|
|
|
if (!mine_mode)
|
|
for (auto module : map->modules()) {
|
|
SubCircuit::Graph mod_graph;
|
|
std::string graph_name = "needle_" + RTLIL::unescape_id(module->name);
|
|
log("Creating needle graph %s.\n", graph_name.c_str());
|
|
if (module2graph(mod_graph, module, constports, min_port_width)) {
|
|
solver.addGraph(graph_name, mod_graph);
|
|
needle_map[graph_name] = module;
|
|
needle_list.push_back(module);
|
|
}
|
|
}
|
|
|
|
for (auto module : design->modules()) {
|
|
SubCircuit::Graph mod_graph;
|
|
std::string graph_name = "haystack_" + RTLIL::unescape_id(module->name);
|
|
log("Creating haystack graph %s.\n", graph_name.c_str());
|
|
if (module2graph(mod_graph, module, constports, -1, design, mine_mode ? mine_max_fanout : -1, mine_mode ? &mine_split : nullptr)) {
|
|
solver.addGraph(graph_name, mod_graph);
|
|
haystack_map[graph_name] = module;
|
|
}
|
|
}
|
|
|
|
if (!mine_mode)
|
|
{
|
|
std::vector<SubCircuit::Solver::Result> results;
|
|
log_header(design, "Running solver from SubCircuit library.\n");
|
|
|
|
std::sort(needle_list.begin(), needle_list.end(), compareSortNeedleList);
|
|
|
|
for (auto needle : needle_list)
|
|
for (auto &haystack_it : haystack_map) {
|
|
log("Solving for %s in %s.\n", ("needle_" + RTLIL::unescape_id(needle->name)).c_str(), haystack_it.first.c_str());
|
|
solver.solve(results, "needle_" + RTLIL::unescape_id(needle->name), haystack_it.first, false);
|
|
}
|
|
log("Found %d matches.\n", GetSize(results));
|
|
|
|
if (results.size() > 0)
|
|
{
|
|
log_header(design, "Substitute SubCircuits with cells.\n");
|
|
|
|
for (int i = 0; i < int(results.size()); i++) {
|
|
auto &result = results[i];
|
|
log("\nMatch #%d: (%s in %s)\n", i, result.needleGraphId.c_str(), result.haystackGraphId.c_str());
|
|
for (const auto &it : result.mappings) {
|
|
log(" %s -> %s", it.first.c_str(), it.second.haystackNodeId.c_str());
|
|
for (const auto & it2 : it.second.portMapping)
|
|
log(" %s:%s", it2.first.c_str(), it2.second.c_str());
|
|
log("\n");
|
|
}
|
|
RTLIL::Cell *new_cell = replace(needle_map.at(result.needleGraphId), haystack_map.at(result.haystackGraphId), result, (min_port_width >= 0));
|
|
design->select(haystack_map.at(result.haystackGraphId), new_cell);
|
|
log(" new cell: %s\n", log_id(new_cell->name));
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
std::vector<SubCircuit::Solver::MineResult> results;
|
|
|
|
log_header(design, "Running miner from SubCircuit library.\n");
|
|
solver.mine(results, mine_cells_min, mine_cells_max, mine_min_freq, mine_limit_mod);
|
|
|
|
map = new RTLIL::Design;
|
|
|
|
int needleCounter = 0;
|
|
for (auto &result: results)
|
|
{
|
|
log("\nFrequent SubCircuit with %d nodes and %d matches:\n", int(result.nodes.size()), result.totalMatchesAfterLimits);
|
|
log(" primary match in %s:", log_id(haystack_map.at(result.graphId)->name));
|
|
for (auto &node : result.nodes)
|
|
log(" %s", RTLIL::unescape_id(node.nodeId).c_str());
|
|
log("\n");
|
|
for (auto &it : result.matchesPerGraph)
|
|
log(" matches in %s: %d\n", log_id(haystack_map.at(it.first)->name), it.second);
|
|
|
|
RTLIL::Module *mod = haystack_map.at(result.graphId);
|
|
std::set<RTLIL::Cell*> cells;
|
|
std::set<RTLIL::Wire*> wires;
|
|
|
|
SigMap sigmap(mod);
|
|
|
|
for (auto &node : result.nodes)
|
|
cells.insert((RTLIL::Cell*)node.userData);
|
|
|
|
for (auto cell : cells)
|
|
for (auto &conn : cell->connections()) {
|
|
RTLIL::SigSpec sig = sigmap(conn.second);
|
|
for (auto &chunk : sig.chunks())
|
|
if (chunk.wire != nullptr)
|
|
wires.insert(chunk.wire);
|
|
}
|
|
|
|
RTLIL::Module *newMod = new RTLIL::Module;
|
|
newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, log_id(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits);
|
|
map->add(newMod);
|
|
|
|
for (auto wire : wires) {
|
|
RTLIL::Wire *newWire = newMod->addWire(wire->name, wire->width);
|
|
newWire->port_input = true;
|
|
newWire->port_output = true;
|
|
}
|
|
|
|
newMod->fixup_ports();
|
|
|
|
for (auto cell : cells) {
|
|
RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type);
|
|
newCell->parameters = cell->parameters;
|
|
for (auto &conn : cell->connections()) {
|
|
std::vector<SigChunk> chunks = sigmap(conn.second);
|
|
for (auto &chunk : chunks)
|
|
if (chunk.wire != nullptr)
|
|
chunk.wire = newMod->wire(chunk.wire->name);
|
|
newCell->setPort(conn.first, chunks);
|
|
}
|
|
}
|
|
}
|
|
|
|
std::ofstream f;
|
|
rewrite_filename(mine_outfile);
|
|
f.open(mine_outfile.c_str(), std::ofstream::trunc);
|
|
if (f.fail())
|
|
log_error("Can't open output file `%s'.\n", mine_outfile.c_str());
|
|
Backend::backend_call(map, &f, mine_outfile, "rtlil");
|
|
f.close();
|
|
}
|
|
|
|
delete map;
|
|
log_pop();
|
|
}
|
|
} ExtractPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|