Emil J. Tywoniak 3da81b2e9d rtlil: Module::clone attaches to source design; callers use clone(dst)		2026-07-20 12:26:39 +02:00
..
abc.cc	rtlil: evacuate src_id_ from AttrObject to per-Design meta vector	2026-07-20 12:26:39 +02:00
abc9.cc	Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7	2026-07-09 08:46:46 +00:00
abc9_exe.cc
abc9_ops.cc	signorm: disable passes that use rewrite_sigspecs	2026-07-17 23:33:02 +02:00
abc_new.cc	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
abc_ops_reintegrate.cc
aigmap.cc
alumacc.cc	twine	2026-07-20 12:26:39 +02:00
arith_tree.cc	WIP	2026-07-17 23:48:54 +02:00
attrmap.cc
attrmvcp.cc
bmuxmap.cc	twine	2026-07-20 12:26:39 +02:00
booth.cc	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
bufnorm.cc	WIP half broken snapshot	2026-07-17 23:32:20 +02:00
bwmuxmap.cc
cellmatch.cc
clkbufmap.cc	signorm: disable in passes that use swap_names	2026-07-17 23:32:34 +02:00
clockgate.cc
CMakeLists.txt
constmap.cc	signorm: disable passes that use rewrite_sigspecs	2026-07-17 23:33:02 +02:00
deminout.cc
demuxmap.cc	twine	2026-07-20 12:26:39 +02:00
dffinit.cc
dfflegalize.cc	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
dfflibmap.cc
dffunmap.cc
extract.cc	rtlil: Module::clone attaches to source design; callers use clone(dst)	2026-07-20 12:26:39 +02:00
extract_counter.cc	twine	2026-07-20 12:26:39 +02:00
extract_fa.cc
extract_reduce.cc
extractinv.cc
filterlib.cc
flowmap.cc	twine	2026-07-20 12:26:39 +02:00
hilomap.cc	signorm: disable passes that use rewrite_sigspecs	2026-07-17 23:33:02 +02:00
insbuf.cc
iopadmap.cc	signorm: disable in passes that use swap_names	2026-07-17 23:32:34 +02:00
libcache.cc
liberty_cache.h	Reformat scl cache.	2026-07-10 14:51:58 +02:00
libparse.cc	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
libparse.h
lut2bmux.cc
lut2mux.cc	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
maccmap.cc
muxcover.cc
nlutmap.cc
pmuxtree.cc
shregmap.cc
simplemap.cc	rtlil: evacuate src_id_ from AttrObject to per-Design meta vector	2026-07-20 12:26:39 +02:00
simplemap.h
techmap.cc	rtlil: Module::clone attaches to source design; callers use clone(dst)	2026-07-20 12:26:39 +02:00
tribuf.cc	twine	2026-07-20 12:26:39 +02:00
zinit.cc