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https://github.com/YosysHQ/yosys
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s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
74 lines
2.4 KiB
Verilog
74 lines
2.4 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// The purpose of these mapping rules is to allow preserve all (sufficiently
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// wide) $shiftx cells during 'techmap' so that they can be mapped to hard
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// resources, rather than being bit-blasted to gates during 'techmap'
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// execution
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module \$shiftx (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] Y;
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
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generate
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if (B_SIGNED) begin
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if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && (_TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0 || _TECHMAP_CONSTVAL_B_[B_WIDTH-1] === 1'bx))
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// Optimisation to remove B_SIGNED if sign bit of B is constant-0
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\$shiftx #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(0),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH-1'd1),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A), .B(B[B_WIDTH-2:0]), .Y(Y)
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);
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else
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wire _TECHMAP_FAIL_ = 1;
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end
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else begin
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if (((A_WIDTH + Y_WIDTH - 1) / Y_WIDTH) < `MIN_MUX_INPUTS)
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wire _TECHMAP_FAIL_ = 1;
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else
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\$__XILINX_SHIFTX #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A), .B(B), .Y(Y)
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);
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end
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endgenerate
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endmodule
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