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56 lines
1.3 KiB
Text
56 lines
1.3 KiB
Text
# has_arst path
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read_verilog << EOT
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module top(input clk, arst, d, output reg q);
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always @(posedge clk or posedge arst)
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if (arst) q <= 0;
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else q <= d;
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endmodule
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EOT
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proc
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async2sync
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select -assert-count 1 w:$auto$async2sync* a:src=* %i
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design -reset
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# has_sr path
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read_verilog << EOT
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module sr(input clk, set, clr, d, output reg q);
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always @(posedge clk or posedge set or posedge clr)
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if (clr) q <= 0;
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else if (set) q <= 1;
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else q <= d;
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endmodule
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EOT
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proc
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async2sync
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select -assert-count 2 w:$auto$async2sync* a:src=* %i
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design -reset
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# has_aload path
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read_verilog << EOT
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module aload(input clk, aload, d, ad, output reg q);
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always @(posedge clk or posedge aload)
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if (aload) q <= ad;
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else q <= d;
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endmodule
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EOT
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proc
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async2sync
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select -assert-count 2 w:$auto$async2sync* a:src=* %i
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design -reset
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# latch path
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read_verilog << EOT
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module latch(input en, arst, d, output reg q);
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always @(*)
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if (arst) q <= 0;
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else if (en) q <= d;
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endmodule
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EOT
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proc
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async2sync
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# latch with async reset path creates 2 wires (new_q + new_d from has_arst handling)
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select -assert-count 2 w:$auto$async2sync* a:src=* %i
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design -reset
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# a latch where has_aload is false (no async load) cannot be tested here
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# because proc optimizes it away into muxes before async2sync runs,
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# leaving no latch cell for async2sync to process.
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