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34 lines
555 B
Text
34 lines
555 B
Text
read_verilog << EOT
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module test (...);
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input [7:1] wa1;
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input [7:1] wa2;
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input [7:0] ra;
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output [7:0] rd;
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input clk;
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input we1, we2;
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input [15:0] wd1, wd2;
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reg [7:0] mem [0:255];
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assign rd = mem[ra];
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always @(posedge clk) begin
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if (we1) begin
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mem[{wa1, 1'b0}] <= wd1[7:0];
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mem[{wa1, 1'b1}] <= wd1[15:8];
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end else begin
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mem[{wa2, 1'b0}] <= wd2[7:0];
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mem[{wa2, 1'b1}] <= wd2[15:8];
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end
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end
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endmodule
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EOT
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proc
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opt
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memory_share
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select -assert-count 1 t:$memwr_v2
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